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soc: samv70: add SAM V70 soc support
Implement soc files for the samv70(b) family devices. Signed-off-by: Perry Hung <[email protected]>
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‎drivers/can/Kconfig.sam‎

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@@ -8,3 +8,15 @@ config CAN_SAM
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bool "Atmel SAM CAN driver"
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default $(dt_compat_enabled,$(DT_COMPAT_ATMEL_SAM_CAN))
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select CAN_MCAN
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if CAN_SAM
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config CAN_MAX_FILTER
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int "Maximum number of concurrent active filters"
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default 5
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range 1 32
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help
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Defines the array size of the callback/msgq pointers.
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Must be at least the size of concurrent reads.
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endif # CAN_SAM

‎drivers/ethernet/Kconfig.sam_gmac‎

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menuconfig ETH_SAM_GMAC
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bool "Atmel SAM Ethernet driver"
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depends on SOC_FAMILY_SAM0 || SOC_FAMILY_SAM
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depends on (SOC_FAMILY_SAM0 || SOC_FAMILY_SAM) && !SOC_SERIES_SAMV70
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select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
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select MDIO
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help

‎drivers/flash/Kconfig.sam‎

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@@ -10,6 +10,6 @@ config SOC_FLASH_SAM
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select FLASH_HAS_DRIVER_ENABLED
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select MPU_ALLOW_FLASH_WRITE if ARM_MPU
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depends on SOC_SERIES_SAME70 || \
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SOC_SERIES_SAMV71
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SOC_SERIES_SAMV71 || SOC_SERIES_SAMV70
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help
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Enable the Atmel SAM series internal flash driver.

‎soc/arm/atmel_sam/samv70/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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soc.c
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soc_config.c
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)

‎soc/arm/atmel_sam/samv70/Kconfig.defconfig.series‎

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# Atmel SAM V70 MCU series configuration options
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# Copyright (c) 2019 Gerson Fernando Budke
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# Copyright (c) 2016 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_SAMV70
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config SOC_SERIES
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default "samv70"
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config SOC_PART_NUMBER
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default "samv70q20" if SOC_PART_NUMBER_SAMV70Q20
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default "samv70q19" if SOC_PART_NUMBER_SAMV70Q19
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default "samv70n20" if SOC_PART_NUMBER_SAMV70N20
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default "samv70n19" if SOC_PART_NUMBER_SAMV70N19
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default "samv70j20" if SOC_PART_NUMBER_SAMV70J20
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default "samv70j19" if SOC_PART_NUMBER_SAMV70J19
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default "samv70q20b" if SOC_PART_NUMBER_SAMV70Q20B
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default "samv70q19b" if SOC_PART_NUMBER_SAMV70Q19B
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default "samv70n20b" if SOC_PART_NUMBER_SAMV70N20B
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default "samv70n19b" if SOC_PART_NUMBER_SAMV70N19B
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default "samv70j20b" if SOC_PART_NUMBER_SAMV70J20B
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default "samv70j19b" if SOC_PART_NUMBER_SAMV70J19B
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#
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# SAM V70 family has in total 71 peripherals capable of generating interrupts
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# for the revision A and 74 for the revision B (not all Peripheral Identifiers
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# are used).
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#
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config NUM_IRQS
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default 74 if SOC_ATMEL_SAMV70_REVB
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default 71
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# Configure default device drivers. If a feature is supported by more than one
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# device driver the default configuration will be placed in the board defconfig
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# file.
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config DMA_SAM_XDMAC
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default y
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depends on DMA
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config ADC_SAM_AFEC
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default y
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depends on ADC
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config I2C_SAM_TWIHS
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default y
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depends on I2C
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config I2S_SAM_SSC
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default y
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depends on I2S
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config USB_DC_SAM_USBHS
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default y
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depends on USB_DEVICE_DRIVER
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config ENTROPY_SAM_RNG
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default y
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depends on ENTROPY_GENERATOR
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config SOC_FLASH_SAM
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default y
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depends on FLASH
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config PWM_SAM
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default y
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depends on PWM
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endif # SOC_SERIES_SAMV70

‎soc/arm/atmel_sam/samv70/Kconfig.series‎

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# Atmel SAM V70 MCU series
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# Copyright (c) 2019 Gerson Fernando Budke
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# Copyright (c) 2016 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_SAMV70
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bool "Atmel SAMV70 MCU"
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select ARM
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select CPU_CORTEX_M7
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select SOC_FAMILY_SAM
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select CPU_HAS_FPU_DOUBLE_PRECISION
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select CPU_CORTEX_M_HAS_CACHE
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select CPU_CORTEX_M_HAS_DWT
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select ASF
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select XIP
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select CPU_HAS_ARM_MPU
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select HAS_SWO
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help
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Enable support for Atmel SAM V70 ARM Cortex-M7 Microcontrollers.
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Part No.: SAMV70J19, SAMV70J20, SAMV70N19, SAMV70N20, SAMV70Q19, SAMV70Q20,
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SAMV70J19B, SAMV70J20B, SAMV70N19B, SAMV70N20B, SAMV70Q19B, SAMV70Q20B

‎soc/arm/atmel_sam/samv70/Kconfig.soc‎

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# Atmel SAM V70 MCU series
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# Copyright (c) 2019 Gerson Fernando Budke
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# Copyright (c) 2016 Piotr Mienkowski
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "Atmel SAMV70 MCU Selection"
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depends on SOC_SERIES_SAMV70
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config SOC_PART_NUMBER_SAMV70Q20
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bool "SAMV70Q20"
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config SOC_PART_NUMBER_SAMV70Q19
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bool "SAMV70Q19"
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config SOC_PART_NUMBER_SAMV70N20
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bool "SAMV70N20"
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config SOC_PART_NUMBER_SAMV70N19
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bool "SAMV70N19"
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config SOC_PART_NUMBER_SAMV70J20
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bool "SAMV70J20"
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config SOC_PART_NUMBER_SAMV70J19
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bool "SAMV70J19"
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config SOC_PART_NUMBER_SAMV70Q20B
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bool "SAMV70Q20B"
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select SOC_ATMEL_SAMV70_REVB
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config SOC_PART_NUMBER_SAMV70Q19B
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bool "SAMV70Q19B"
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select SOC_ATMEL_SAMV70_REVB
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config SOC_PART_NUMBER_SAMV70N20B
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bool "SAMV70N20B"
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select SOC_ATMEL_SAMV70_REVB
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config SOC_PART_NUMBER_SAMV70N19B
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bool "SAMV70N19B"
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select SOC_ATMEL_SAMV70_REVB
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config SOC_PART_NUMBER_SAMV70J20B
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bool "SAMV70J20B"
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select SOC_ATMEL_SAMV70_REVB
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config SOC_PART_NUMBER_SAMV70J19B
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bool "SAMV70J19B"
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select SOC_ATMEL_SAMV70_REVB
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endchoice
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if SOC_SERIES_SAMV70
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config SOC_ATMEL_SAMV70_REVB
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bool
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config SOC_ATMEL_SAMV70_EXT_SLCK
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bool "Use external crystal oscillator for slow clock"
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help
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Say y if you want to use external 32 kHz crystal
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oscillator to drive the slow clock. Note that this
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adds a few seconds to boot time, as the crystal
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needs to stabilize after power-up.
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Says n if you do not need accurate and precise timers.
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The slow clock will be driven by the internal fast
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RC oscillator running at 32 kHz.
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config SOC_ATMEL_SAMV70_EXT_MAINCK
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bool "Use external crystal oscillator for main clock"
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help
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The main clock is being used to drive the PLL, and
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thus driving the processor clock.
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Say y if you want to use external crystal oscillator
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to drive the main clock. Note that this adds about
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a second to boot time, as the crystal needs to
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stabilize after power-up.
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The crystal used here can be from 3 to 20 MHz.
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Says n here will use the internal fast RC oscillator
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running at 12 MHz.
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config SOC_ATMEL_SAMV70_MDIV
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int "MDIV"
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default 2
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range 1 4
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help
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This divisor defines a ratio between processor clock (HCLK)
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and master clock (MCK):
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MCK = HCLK / MDIV
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config SOC_ATMEL_SAMV70_PLLA_MULA
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int "PLL MULA"
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default 24
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range 1 62
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help
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This is the multiplier MULA used by the PLL.
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The processor clock is (MAINCK * (MULA + 1) / DIVA).
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Board config file can override this settings
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for a particular board.
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Setting MULA=0 would disable PLL at boot, this is currently
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not supported.
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With default of MULA == 24, and DIVA == 1,
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PLL is running at 25 times the main clock frequency.
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config SOC_ATMEL_SAMV70_PLLA_DIVA
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int "PLL DIVA"
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default 1
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range 1 255
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help
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This is the divider DIVA used by the PLL.
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The processor clock is (MAINCK * (MULA + 1) / DIVA).
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Board config file can override this settings
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for a particular board.
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Setting DIVA=0 would disable PLL at boot, this is currently
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not supported.
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With default of MULA == 24, and DIVA == 1,
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PLL is running at 25 times the main clock frequency.
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config SOC_ATMEL_SAMV70_WAIT_MODE
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bool "Go to Wait mode instead of Sleep mode"
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depends on SOC_ATMEL_SAMV70_EXT_MAINCK
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default y if DEBUG
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help
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For JTAG debugging CPU clock (HCLK) should not stop. In order
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to achieve this, make CPU go to Wait mode instead of Sleep
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mode while using external crystal oscillator for main clock.
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config SOC_ATMEL_SAMV70_DISABLE_ERASE_PIN
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bool "Disable ERASE pin"
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help
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At reset ERASE pin is configured in System IO mode. Asserting the ERASE
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pin at '1' will completely erase Flash memory. Setting this option will
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switch the pin to general IO mode giving control of the pin to the GPIO
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module.
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endif # SOC_SERIES_SAMV70

‎soc/arm/atmel_sam/samv70/linker.ld‎

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/* linker.ld - Linker command/script file */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

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