tests: arm: sw_vector_table: enhance test configs for frdm_mcxa166

irq 0 in frdm_mcxa166/276 are reserved can not used for testing.
add a config to shift test irq, also add support for rt700
also fix irq1 issue on mimxrt1180 as it is a debug trace interrupt

fixes: #92877, #92521

Signed-off-by: Hake Huang <[email protected]>

Author: hakehuang

tests/arch/arm/arm_irq_vector_table/Kconfig

@@ -4,4 +4,8 @@ config NUM_IRQS
 	int "Number of IRQs for this test, made overridable in the .conf file"
 	default 3
 
+config ISR_OFFSET
+	int "isr offset from vector table"
+	default 0
+
 source "Kconfig.zephyr"

tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa166.conf

@@ -0,0 +1 @@
+CONFIG_ISR_OFFSET=39

tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa276.conf

@@ -0,0 +1 @@
+CONFIG_ISR_OFFSET=39

tests/arch/arm/arm_irq_vector_table/boards/mimxrt1180_evk_mimxrt1189_cm33.conf

@@ -0,0 +1 @@
+CONFIG_ISR_OFFSET=4

tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c

@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/kernel.h>
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
 #include <cmsis_core.h>
@@ -13,7 +14,7 @@
  * Offset (starting from the beginning of the vector table)
  * of the location where the ISRs will be manually installed.
  */
-#define _ISR_OFFSET 0
+#define _ISR_OFFSET CONFIG_ISR_OFFSET
 
 #if defined(CONFIG_SOC_FAMILY_NORDIC_NRF)
 #undef _ISR_OFFSET
@@ -108,7 +109,8 @@ ZTEST(vector_table, test_arm_irq_vector_table)
 		      k_sem_take(&sem[2], K_NO_WAIT)));
 
 	for (int ii = 0; ii < 3; ii++) {
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || defined(CONFIG_SOC_TI_LM3S6965_QEMU)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || defined(CONFIG_SOC_TI_LM3S6965_QEMU) || \
+	defined(CONFIG_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 		/* the QEMU does not simulate the
 		 * STIR register: this is a workaround
 		 */
@@ -242,7 +244,23 @@ const vth __irq_vector_table _irq_vector_table[] = {
 #error "GPT timer enabled, but no known SOC selected. ISR table needs rework"
 #endif
 #else
-const vth __irq_vector_table _irq_vector_table[] = {isr0, isr1, isr2};
+
+#if defined(CONFIG_MCUX_OS_TIMER)
+extern void mcux_lpc_ostick_isr(void);
+#define TIMER_IRQ_NUM DT_IRQN(DT_INST(0, nxp_os_timer))
+#define TIMER_IRQ_HANDLER mcux_lpc_ostick_isr
+#define IRQ_VECTOR_TABLE_SIZE _ISR_OFFSET > TIMER_IRQ_NUM ? (_ISR_OFFSET + 3) : (TIMER_IRQ_NUM + 1)
+#else
+#define IRQ_VECTOR_TABLE_SIZE (_ISR_OFFSET + 3)
+#endif /* CONFIG_MCUX_OS_TIMER */
+const vth __irq_vector_table _irq_vector_table[IRQ_VECTOR_TABLE_SIZE] = {
+	[_ISR_OFFSET] = isr0,
+	[_ISR_OFFSET + 1] = isr1,
+	[_ISR_OFFSET + 2] = isr2,
+#ifndef CONFIG_CORTEX_M_SYSTICK
+	[TIMER_IRQ_NUM] = TIMER_IRQ_HANDLER,
+#endif
+};
 #endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */
 
 /**