boards: arm: stm32h7b3i_dk: add support for display

Update board device tree with LTDC node
Update board documentation - display support and RGB pinout
Update board defconfig - if display is used, then external
SDRAM must be enabled in order to fit the frame buffer in
memory

Signed-off-by: Tomislav Milkovic <[email protected]>

Author: tmilkovic51

boards/arm/stm32h7b3i_dk/Kconfig.defconfig

@@ -8,10 +8,21 @@ if BOARD_STM32H7B3I_DK
 config BOARD
 	default "stm32h7b3i_dk"
 
+config KSCAN
+	default y if DISPLAY
+
 config I2C
 	default y if KSCAN
 
 config KSCAN_FT5336
 	default y if KSCAN
 
+config KSCAN_FT5336_INTERRUPT
+	default y if KSCAN_FT5336
+
+# MEMC needs to be enabled in order to store
+# display buffer to external SDRAM connected to FMC
+config MEMC
+	default y if DISPLAY
+
 endif # BOARD_STM32H7B3I_DK

boards/arm/stm32h7b3i_dk/doc/index.rst

@@ -62,6 +62,8 @@ The current Zephyr stm32h7b3i_dk board configuration supports the following hard
 +-----------+------------+-------------------------------------+
 | FMC       | on-chip    | memc (SDRAM)                        |
 +-----------+------------+-------------------------------------+
+| LTDC      | on-chip    | display                             |
++-----------+------------+-------------------------------------+
 
 
 Other hardware features have not been enabled yet for this board.
@@ -92,6 +94,11 @@ Default Zephyr Peripheral Mapping:
     - SDNRAS/SDNCAS : PF11/PG15
     - NBL0/NBL1 : PE0/PE1
     - SDCLK/SDNWE/SDCKE1/SDNE1 : PG8/PH5/PH7/PH6
+- LTDC :
+    - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6
+    - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2
+    - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6
+    - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13
 
 
 System Clock

boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts

@@ -7,6 +7,7 @@
 /dts-v1/;
 #include <st/h7/stm32h7b3Xi.dtsi>
 #include <st/h7/stm32h7b3lihxq-pinctrl.dtsi>
+#include <dt-bindings/display/stm32_ltdc.h>
 #include "arduino_r3_connector.dtsi"
 
 / {
@@ -18,6 +19,7 @@
 		zephyr,shell-uart = &usart1;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
+		zephyr,display = &ltdc;
 	};
 
 	leds {
@@ -170,3 +172,34 @@
 	cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
 	status = "okay";
 };
+
+&ltdc {
+	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
+		     &ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
+		     &ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
+		     &ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
+		     &ltdc_b0_pj12 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
+		     &ltdc_b4_pk3 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
+		     &ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi12 &ltdc_vsync_pi13>;
+	pinctrl-names = "default";
+	disp-on-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>;
+	bl-ctrl-gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>;
+	ext-sdram = <&sdram2>;
+	status = "okay";
+
+	width = <480>;
+	height = <272>;
+	hsync-pol = <STM32_LTDC_HSPOL_ACTIVE_LOW>;
+	vsync-pol = <STM32_LTDC_VSPOL_ACTIVE_LOW>;
+	de-pol = <STM32_LTDC_DEPOL_ACTIVE_LOW>;
+	pclk-pol = <STM32_LTDC_PCPOL_ACTIVE_LOW>;
+	hsync-duration = <1>;
+	vsync-duration = <10>;
+	hbp-duration = <43>;
+	vbp-duration = <12>;
+	hfp-duration = <8>;
+	vfp-duration = <4>;
+	def-back-color-red = <0xFF>;
+	def-back-color-green = <0xFF>;
+	def-back-color-blue = <0xFF>;
+};

boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.yaml

@@ -16,3 +16,4 @@ supported:
   - kscan:touch
   - memc
   - backup_sram
+  - display