drivers: spi: Initial support for RZ/G3S

Add SPI driver support for Renesas RZ/G3S

Signed-off-by: Quang Le <[email protected]>
Signed-off-by: Binh Nguyen <[email protected]>

Author: le-quang168

drivers/spi/CMakeLists.txt

@@ -49,6 +49,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6 spi_psoc6.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_PW spi_pw.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_RENESAS_RA spi_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_RENESAS_RA8 spi_b_renesas_ra8.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_RENESAS_RZ_RSPI spi_renesas_rz_rspi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_RPI_PICO_PIO spi_rpi_pico_pio.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_RV32M1_LPSPI spi_rv32m1_lpspi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_SAM spi_sam.c)

drivers/spi/Kconfig

@@ -126,6 +126,7 @@ source "drivers/spi/Kconfig.psoc6"
 source "drivers/spi/Kconfig.pw"
 source "drivers/spi/Kconfig.renesas_ra"
 source "drivers/spi/Kconfig.renesas_ra8"
+source "drivers/spi/Kconfig.renesas_rz"
 source "drivers/spi/Kconfig.rpi_pico"
 source "drivers/spi/Kconfig.rv32m1_lpspi"
 source "drivers/spi/Kconfig.sam"

drivers/spi/Kconfig.renesas_rz

@@ -0,0 +1,44 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SPI_RENESAS_RZ_RSPI
+	bool "Renesas RZ RSPI SPI"
+	default y
+	depends on DT_HAS_RENESAS_RZ_RSPI_ENABLED
+	select USE_RZ_FSP_RSPI_SPI
+	select PINCTRL
+	help
+	  Enable Renesas RZ RSPI SPI Driver.
+
+if SPI_RENESAS_RZ_RSPI
+
+config SPI_RENESAS_RZ_RSPI_INTERRUPT
+	bool "RZ RSPI Interrupt Support"
+	help
+	  Enable Interrupt support for the RSPI.
+
+config SPI_RENESAS_RZ_RSPI_DMAC
+	bool "RZ SPI DMA Support"
+	select USE_RZ_FSP_DMA
+	help
+	  Enable the SPI DMA mode for SPI instances
+
+if SPI_RTIO
+config SPI_RTIO_SQ_SIZE
+	int "Number of available submission queue entries"
+	default 8 # Sensible default that covers most common spi transactions
+	help
+	  When RTIO is use with SPI each driver holds a context with which blocking
+	  API calls use to perform SPI transactions. This queue needs to be as deep
+	  as the longest set of spi_buf_sets used, where normal SPI operations are
+	  used (equal length buffers). It may need to be slightly deeper where the
+	  spi buffer sets for transmit/receive are not always matched equally in
+	  length as these are transformed into normal transceives.
+
+config SPI_RTIO_CQ_SIZE
+	int "Number of available completion queue entries"
+	default 8 # Sensible default that covers most common spi transactions
+
+endif # SPI_RTIO
+
+endif # SPI_RENESAS_RZ_RSPI