boards: frdm_mcxn236: Support sai for NXP frdm_mcxn236

1. Support sai for NXP frdm_mcxn236.
2. Verified tests/drivers/i2s/i2s_speed

Signed-off-by: Neil Chen <[email protected]>

Author: NeilChen93

boards/nxp/frdm_mcxn236/board.c

@@ -103,21 +103,18 @@ void board_early_init_hook(void)
 
 	CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1))
-	/* Set up PLL1 for 80 MHz FlexCAN clock */
-	const pll_setup_t pll1Setup = {
-		.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) |
-			   SCG_SPLLCTRL_SELP(13U),
-		.pllndiv = SCG_SPLLNDIV_NDIV(3U),
-		.pllpdiv = SCG_SPLLPDIV_PDIV(1U),
-		.pllmdiv = SCG_SPLLMDIV_MDIV(10U),
-		.pllRate = 80000000U
-	};
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+	/* < Set up PLL1 */
+	const pll_setup_t pll1_Setup = {
+		.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
+				 SCG_SPLLCTRL_SELP(1U),
+		.pllndiv = SCG_SPLLNDIV_NDIV(25U),
+		.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
+		.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
+		.pllRate = 24576000U};
 
 	/* Configure PLL1 to the desired values */
-	CLOCK_SetPLL1Freq(&pll1Setup);
-	/* PLL1 Monitor is disabled */
-	CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);
+	CLOCK_SetPLL1Freq(&pll1_Setup);
 	/* Set PLL1 CLK0 divider to value 1 */
 	CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
 #endif
@@ -216,7 +213,7 @@ void board_early_init_hook(void)
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan1))
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcan1Clk, 1U);
-	CLOCK_AttachClk(kPLL1_CLK0_to_FLEXCAN1);
+	CLOCK_AttachClk(kFRO_HF_to_FLEXCAN1);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(vref))
@@ -330,6 +327,18 @@ void board_early_init_hook(void)
 	CLOCK_EnableClock(kCLOCK_Ewm0);
 #endif
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0))
+	CLOCK_SetClkDiv(kCLOCK_DivSai0Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI0);
+	CLOCK_EnableClock(kCLOCK_Sai0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+	CLOCK_SetClkDiv(kCLOCK_DivSai1Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI1);
+	CLOCK_EnableClock(kCLOCK_Sai1);
+#endif
+
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
 }

boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi

@@ -207,4 +207,29 @@
 			input-enable;
 		};
 	};
+
+	pinmux_sai0: pinmux_sai0 {
+		group0 {
+			pinmux = <SAI0_TXD0_PIO3_10>,
+				<SAI0_TX_BCLK_PIO3_8>,
+				<SAI0_TX_FS_PIO3_9>;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
+	pinmux_sai1: pinmux_sai1 {
+		group0 {
+			pinmux = <SAI1_TX_BCLK_PIO3_16>,
+				<SAI1_TX_FS_PIO3_17>,
+				<SAI1_TXD0_PIO2_8>,
+				<SAI1_RX_FS_PIO1_7>,
+				<SAI1_RX_BCLK_PIO3_18>,
+				<SAI1_RXD0_PIO2_9>;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
 };

boards/nxp/frdm_mcxn236/frdm_mcxn236.dts

@@ -404,3 +404,15 @@ p3t1755dp_ard_i2c_interface: &flexcomm5_lpi2c5 {};
 
 dvp_20pin_i2c: &flexcomm2_lpi2c2 {};
 dvp_20pin_interface: &video_sdma {};
+
+&sai0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_sai0>;
+	pinctrl-names = "default";
+};
+
+&sai1 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_sai1>;
+	pinctrl-names = "default";
+};

boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml

@@ -21,6 +21,7 @@ supported:
   - flash
   - gpio
   - i2c
+  - i2s
   - i3c
   - pwm
   - regulator

dts/arm/nxp/nxp_mcxn23x_common.dtsi

@@ -924,6 +924,40 @@
 		interrupts = <100 0>;
 		clk-divider = <0x0>;
 	};
+
+	sai0: sai@106000 {
+		compatible = "nxp,mcux-i2s";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#pinmux-cells = <2>;
+		reg = < 0x106000 0x1000>;
+		clocks = <&syscon MCUX_SAI0_CLK>;
+		pinmuxes = <&sai0 0x100 0x40000000>;
+		interrupts = <59 0>;
+		dmas = <&edma0 0 99>, <&edma0 0 100>;
+		dma-names = "rx", "tx";
+		nxp,tx-channel = <1>;
+		nxp,tx-dma-channel = <0>;
+		nxp,rx-dma-channel = <1>;
+		status = "disabled";
+	};
+
+	sai1: sai@107000 {
+		compatible = "nxp,mcux-i2s";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#pinmux-cells = <2>;
+		reg = < 0x107000 0x1000>;
+		clocks = <&syscon MCUX_SAI1_CLK>;
+		pinmuxes = <&sai1 0x100 0x40000000>;
+		interrupts = <60 0>;
+		dmas = <&edma0 0 101>, <&edma0 0 102>;
+		dma-names = "rx", "tx";
+		nxp,tx-channel = <1>;
+		nxp,tx-dma-channel = <2>;
+		nxp,rx-dma-channel = <3>;
+		status = "disabled";
+	};
 };
 
 &systick {

tests/drivers/i2s/i2s_api/testcase.yaml

@@ -12,6 +12,7 @@ tests:
       - mimxrt685_evk/mimxrt685s/cm33
       - nrf54h20dk/nrf54h20/cpuapp
       - mimxrt1060_evk/mimxrt1062/qspi
+      - frdm_mcxn236/mcxn236
   drivers.i2s.gpio_loopback:
     depends_on:
       - i2s
@@ -27,6 +28,7 @@ tests:
       - mimxrt595_evk/mimxrt595s/cm33
       - mimxrt685_evk/mimxrt685s/cm33
       - nrf54h20dk/nrf54h20/cpuapp
+      - frdm_mcxn236/mcxn236
     harness_config:
       fixture: gpio_loopback
   drivers.i2s.gpio_loopback.nrf54h:

tests/drivers/i2s/i2s_speed/Readme.txt

@@ -46,3 +46,10 @@ These are the HW changes required to run this test on MIMXRT1060-EVK[B/C]:
 
 - NOTE: these connections cause contention with the following signals/features:
 	- camera CSI_D[2-7]
+
+FRDM-MCXN236:
+This board uses CONFIG_I2S_TEST_SEPARATE_DEVICES=y and connects two SAI peripherals by shorting
+signals externally on the EVK.  These are the HW changes required to run this test:
+        - Short BCLK J1-pin9  (SAI1_RX_BCLK/P3_18) to J8-pin25 (SAI0_TX_BCLK/P3_8)
+        - Short SYNC J1-pin13 (SAI1_RX_FS/P1_7)    to J8-pin26 (SAI0_TX_FS/P3_9)
+        - Short Data J1-pin15 (SAI1_RXD0/P2_9)     to J8-pin27  (SAI0_TXD0/P3_10)

tests/drivers/i2s/i2s_speed/boards/frdm_mcxn236.conf

@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2024, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# SAI peripheral does not have loopback mode.  Use 2 SAI peripherals connected
+# together externally.
+CONFIG_I2S_TEST_SEPARATE_DEVICES=y
+
+# CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs)
+# together, and should be sized as needed by the application.  If not large
+# enough, the DMA may starve.  Symptoms of this issue include transmit blocks
+# repeated, or RX blocks skipped. For I2S driver, queue size must be at least 3.
+CONFIG_DMA_TCD_QUEUE_SIZE=4
+
+# Repeat test continually to help find intermittent issues
+CONFIG_ZTEST_RETEST_IF_PASSED=y
+
+# I2S and DMA logging can occur in interrupt context, and interfere with I2S
+# stream timing.  If using either logging, set logging to deferred
+# CONFIG_LOG_MODE_DEFERRED=y
+
+CONFIG_DMA_LOG_LEVEL_OFF=y
+CONFIG_I2S_LOG_LEVEL_OFF=y
+CONFIG_I2S_TEST_USE_GPIO_LOOPBACK=y

tests/drivers/i2s/i2s_speed/boards/frdm_mcxn236.overlay

@@ -0,0 +1,15 @@
+/* i2s_speed with CONFIG_I2S_TEST_SEPARATE_DEVICES=y uses two I2S peripherals:
+ * i2s-node0 is the receiver
+ * i2s-node1 is the transmitter
+ */
+
+/ {
+	aliases {
+		i2s-node0 = &sai1;
+		i2s-node1 = &sai0;
+	};
+};
+
+&sai0 {
+	mclk-output;
+};