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125 | 125 | compatible = "atmel,sam0-dmac"; |
126 | 126 | reg = <0x4100A000 0x50>; |
127 | 127 | interrupts = <31 0>, <32 0>, <33 0>, <34 0>, <35 0>; |
| 128 | + status = "disabled"; |
128 | 129 |
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129 | 130 | #dma-cells = <2>; |
130 | 131 | }; |
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315 | 316 | interrupt-names = "overrun", "resrdy"; |
316 | 317 | clocks = <&gclk 40>, <&mclk 0x20 7>; |
317 | 318 | clock-names = "GCLK", "MCLK"; |
| 319 | + status = "disabled"; |
318 | 320 |
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319 | 321 | #io-channel-cells = <1>; |
320 | 322 |
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336 | 338 | interrupt-names = "overrun", "resrdy"; |
337 | 339 | clocks = <&gclk 41>, <&mclk 0x20 8>; |
338 | 340 | clock-names = "GCLK", "MCLK"; |
| 341 | + status = "disabled"; |
339 | 342 |
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340 | 343 | #io-channel-cells = <1>; |
341 | 344 |
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356 | 359 | interrupts = <107 0>; |
357 | 360 | clocks = <&gclk 9>, <&mclk 0x14 14>; |
358 | 361 | clock-names = "GCLK", "MCLK"; |
| 362 | + status = "disabled"; |
359 | 363 | }; |
360 | 364 |
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361 | 365 | tc2: tc@4101a000 { |
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364 | 368 | interrupts = <109 0>; |
365 | 369 | clocks = <&gclk 26>, <&mclk 0x18 13>; |
366 | 370 | clock-names = "GCLK", "MCLK"; |
| 371 | + status = "disabled"; |
367 | 372 | }; |
368 | 373 |
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369 | 374 | tc4: tc@42001400 { |
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372 | 377 | interrupts = <111 0>; |
373 | 378 | clocks = <&gclk 30>, <&mclk 0x1c 5>; |
374 | 379 | clock-names = "GCLK", "MCLK"; |
| 380 | + status = "disabled"; |
375 | 381 | }; |
376 | 382 |
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377 | 383 | tc6: tc@43001400 { |
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380 | 386 | interrupts = <113 0>; |
381 | 387 | clocks = <&gclk 39>, <&mclk 0x20 5>; |
382 | 388 | clock-names = "GCLK", "MCLK"; |
| 389 | + status = "disabled"; |
383 | 390 | }; |
384 | 391 |
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385 | 392 | tcc0: tcc@41016000 { |
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389 | 396 | <90 0>, <91 0>; |
390 | 397 | clocks = <&gclk 25>, <&mclk 0x18 11>; |
391 | 398 | clock-names = "GCLK", "MCLK"; |
| 399 | + status = "disabled"; |
392 | 400 |
|
393 | 401 | channels = <6>; |
394 | 402 | counter-size = <24>; |
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400 | 408 | interrupts = <92 0>, <93 0>, <94 0>, <95 0>, <96 0>; |
401 | 409 | clocks = <&gclk 25>, <&mclk 0x18 12>; |
402 | 410 | clock-names = "GCLK", "MCLK"; |
| 411 | + status = "disabled"; |
403 | 412 |
|
404 | 413 | channels = <4>; |
405 | 414 | counter-size = <24>; |
|
411 | 420 | interrupts = <97 0>, <98 0>, <99 0>, <100 0>; |
412 | 421 | clocks = <&gclk 29>, <&mclk 0x1c 3>; |
413 | 422 | clock-names = "GCLK", "MCLK"; |
| 423 | + status = "disabled"; |
414 | 424 |
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415 | 425 | channels = <3>; |
416 | 426 | counter-size = <16>; |
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422 | 432 | interrupts = <101 0>, <102 0>, <103 0>; |
423 | 433 | clocks = <&gclk 29>, <&mclk 0x1c 4>; |
424 | 434 | clock-names = "GCLK", "MCLK"; |
| 435 | + status = "disabled"; |
425 | 436 |
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426 | 437 | channels = <2>; |
427 | 438 | counter-size = <16>; |
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433 | 444 | interrupts = <104 0>, <105 0>, <106 0>; |
434 | 445 | clocks = <&gclk 38>, <&mclk 0x20 4>; |
435 | 446 | clock-names = "GCLK", "MCLK"; |
| 447 | + status = "disabled"; |
436 | 448 |
|
437 | 449 | channels = <2>; |
438 | 450 | counter-size = <16>; |
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