soc: renesas: rx: Update OFS value in vects.c using Kconfig

OFS values setting for RXv1/RXv2 will be defined in SOC
Kconfig and set in vects.c file

Signed-off-by: Quy Tran <[email protected]>

Author: quytranpzz

arch/rx/core/vects.c

@@ -8,7 +8,7 @@
 #include <zephyr/irq.h>
 #include <kswap.h>
 #include <zephyr/tracing/tracing.h>
-#include <zephyr/drivers/clock_control/renesas_rx_cgc.h>
+#include <ofsm.h>
 
 typedef void (*fp)(void);
 extern void _start(void);
@@ -19,20 +19,22 @@ extern void z_rx_irq_exit(void);
 #define CONFIG_GEN_IRQ_START_VECTOR 0
 #endif
 
+#ifndef SOC_RX_MDE
+#define SOC_RX_MDE (0xFFFFFFFFUL)
+#endif
+#ifndef SOC_RX_OFS0
+#define SOC_RX_OFS0 (0xFFFFFFFFUL)
+#endif
+#ifndef SOC_RX_OFS1
+#define SOC_RX_OFS1 (0xFFFFFFFFUL)
+#endif
+
 #define EXVECT_SECT __attribute__((section(".exvectors")))
 #define RVECT_SECT  __attribute__((section(".rvectors")))
 #define FVECT_SECT  __attribute__((section(".fvectors")))
 
 #define __ISR__ __attribute__((interrupt, naked))
 
-#define SET_OFS1_HOCO_BITS(reg, freq)                                                              \
-	((reg) & ~(0b11 << 12)) | ((((freq) == 24000000   ? 0b10                                   \
-				     : (freq) == 32000000 ? 0b11                                   \
-				     : (freq) == 48000000 ? 0b01                                   \
-				     : (freq) == 64000000 ? 0b00                                   \
-							  : 0b11)                                  \
-				    << 12))
-
 static ALWAYS_INLINE void REGISTER_SAVE(void)
 {
 	__asm volatile(
@@ -430,12 +432,10 @@ INT_DEMUX(255);
 const void *FixedVectors[] FVECT_SECT = {
 	/* 0x00-0x4c: Reserved, must be 0xff (according to e2 studio example) */
 	/* Reserved for OFSM */
+	(fp)SOC_RX_MDE,
 	(fp)0xFFFFFFFF,
-	(fp)0xFFFFFFFF,
-	(fp)(SET_OFS1_HOCO_BITS(
-		0xFFFFFFFF,
-		(RX_CGC_PROP_HAS_STATUS_OKAY_OR(DT_NODELABEL(hoco), clock_frequency, 32000000)))),
-	(fp)0xFFFFFFFF,
+	(fp)SOC_RX_OFS1,
+	(fp)SOC_RX_OFS0,
 	/* Reserved area */
 	(fp)0xFFFFFFFF,
 	(fp)0xFFFFFFFF,
@@ -490,10 +490,10 @@ const FVECT_SECT void *resetVector = _start;
  */
 const void *ExceptVectors[] EXVECT_SECT = {
 	/* 0x00-0x4c: Reserved, must be 0xff (according to e2 studio example) */
+	(fp)SOC_RX_MDE,
 	(fp)0xFFFFFFFF,
-	(fp)0xFFFFFFFF,
-	(fp)0xFFFFFFFF,
-	(fp)0xFFFFFFFF,
+	(fp)SOC_RX_OFS1,
+	(fp)SOC_RX_OFS0,
 	(fp)0xFFFFFFFF,
 	(fp)0xFFFFFFFF,
 	(fp)0xFFFFFFFF,

soc/renesas/rx/rx130/ofsm.c

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Option setting header file for Renesas RX130
+ */
+
+/*
+ * Option-Setting Memory for the RX. This region of memory (located in flash)
+ * determines the state of the MCU after reset and can not be changed on runtime
+ *
+ * All registers are set to 0xffffffff by default, which are "safe" settings.
+ * Please refer to the Renesas RX Group User's Manual before changing any of
+ * the values as some changes can be permanent or lock access to the device.
+ *
+ * Address range: 0xFFFFFF80 to 0xFFFFFF8F
+ */
+
+/* Endian Select Register (MDE) at 0xFFFFFF80
+ *
+ * b2 to b0: endian select between (0 0 0) for big endian and (1 1 1) for little
+ * endian. Set this according to __BYTE_ORDER__ (cf. include\toolchain\gcc.h)
+ *
+ * all other bits are reserved and have to be set to 1
+ */
+#define SOC_RX_MDE (0xFFFFFFFFUL) /* little endian */
+
+/* Option Function Select Register 0 (OFS0)
+ * This section sets the IWDT (Independent Watchdog Timer) behavior immediately after reset
+ * by programming the OFS0 register. When enabled, IWDT starts counting automatically
+ * starts after a reset.
+ */
+#define SOC_RX_OFS0 (0xFFFFFFFFUL)
+
+/* Option Function Select Register 1 (OFS1) (Voltage detection and HOCO)
+ */
+#define SOC_RX_OFS1 (0xFFFFFFFFUL)

soc/renesas/rx/rx130/ofsm.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Option setting header file for Renesas RX261
+ */
+
+#include <zephyr/devicetree.h>
+
+/*
+ * Option-Setting Memory for the RX. This region of memory (located in flash)
+ * determines the state of the MCU after reset and can not be changed on runtime
+ *
+ * All registers are set to 0xffffffff by default, which are "safe" settings.
+ * Please refer to the Renesas RX Group User's Manual before changing any of
+ * the values as some changes can be permanent or lock access to the device.
+ *
+ * Address range: 0xFFFFFF80 to 0xFFFFFF8F
+ */
+
+/* Endian Select Register (MDE) at 0xFFFFFF80
+ *
+ * b2 to b0: endian select between (0 0 0) for big endian and (1 1 1) for little
+ * endian. Set this according to __BYTE_ORDER__ (cf. include\toolchain\gcc.h)
+ *
+ * all other bits are reserved and have to be set to 1
+ */
+#define SOC_RX_MDE (0xFFFFFFFFUL) /* little endian */
+
+/* Option Function Select Register 0 (OFS0)
+ * This section sets the IWDT (Independent Watchdog Timer) behavior immediately after reset
+ * by programming the OFS0 register. When enabled, IWDT starts counting automatically
+ * starts after a reset.
+ */
+#define SOC_RX_OFS0 (0xFFFFFFFFUL)
+
+/* Option Function Select Register 1 (OFS1) (Voltage detection and HOCO)
+ */
+
+#define RX_HOCO_FREQ DT_PROP(DT_NODELABEL(hoco), clock_frequency)
+
+#if (RX_HOCO_FREQ == 24000000)
+#define SOC_OFS1_HOCO 0b10
+#elif (RX_HOCO_FREQ == 32000000)
+#define SOC_OFS1_HOCO 0b11
+#elif (RX_HOCO_FREQ == 48000000)
+#define SOC_OFS1_HOCO 0b01
+#elif (RX_HOCO_FREQ == 64000000)
+#define SOC_OFS1_HOCO 0b00
+#else
+#error "Unsupported HOCO clock frequency (must be 24/32/48/64 MHz)"
+#endif
+
+#define SOC_RX_OFS1 ((SOC_OFS1_HOCO << 12) | 0xFFFFCFFFUL)