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drivers: clock: ti: Add initial support TI MSPM0 clock module
Add initial support TI MSPM0 clock module Signed-off-by: Saravanan Sekar <[email protected]> Signed-off-by: Jackson Farley <[email protected]>
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‎drivers/clock_control/CMakeLists.txt

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@@ -19,6 +19,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG clock_cont
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG_K4 clock_control_mcux_scg_k4.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SYSCON clock_control_mcux_syscon.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MSPM0 clock_control_mspm0.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCM clock_control_npcm.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCX clock_control_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_control_nrf.c)

‎drivers/clock_control/Kconfig

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@@ -50,6 +50,8 @@ source "drivers/clock_control/Kconfig.mcux_sim"
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source "drivers/clock_control/Kconfig.mcux_syscon"
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source "drivers/clock_control/Kconfig.mspm0"
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source "drivers/clock_control/Kconfig.npcm"
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source "drivers/clock_control/Kconfig.npcx"

‎drivers/clock_control/Kconfig.mspm0

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# TI MSPM0 Family
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# Copyright (c) 2025, Texas Instruments Inc.
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_MSPM0
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bool "TI MSPM0 clock"
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default y
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depends on SOC_FAMILY_TI_MSPM0
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help
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This option enables the TI MSPM0 Clock Control Enabler

‎drivers/clock_control/clock_control_mspm0.c

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/*
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* Copyright (c) 2025 Texas Instruments
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* Copyright (c) 2025 Linumiz
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/mspm0_clock_control.h>
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#include <ti/driverlib/driverlib.h>
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#include <string.h>
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#define MSPM0_ULPCLK_DIV COND_CODE_1( \
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DT_NODE_HAS_PROP(DT_NODELABEL(ulpclk), clk_div), \
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(CONCAT(DL_SYSCTL_ULPCLK_DIV_, \
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DT_PROP(DT_NODELABEL(ulpclk), clk_div))), \
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(0))
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#define MSPM0_MCLK_DIV COND_CODE_1( \
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DT_NODE_HAS_PROP(DT_NODELABEL(mclk), clk_div), \
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(CONCAT(DL_SYSCTL_MCLK_DIVIDER_, \
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DT_PROP(DT_NODELABEL(mclk), clk_div))), \
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(0))
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#define MSPM0_MFPCLK_DIV COND_CODE_1( \
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DT_NODE_HAS_PROP(DT_NODELABEL(mfpclk), clk_div), \
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(CONCAT(DL_SYSCTL_HFCLK_MFPCLK_DIVIDER_, \
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DT_PROP(DT_NODELABEL(mfpclk), clk_div))), \
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(0))
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(mfpclk), okay)
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#define MSPM0_MFPCLK_ENABLED 1
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
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#define MSPM0_PLL_ENABLED 1
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#endif
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#define DT_MCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(mclk))
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#define DT_LFCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(lfclk))
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#define DT_HSCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(hsclk))
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#define DT_HFCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(hfclk))
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#define DT_MFPCLK_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(mfpclk))
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#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
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struct mspm0_clk_cfg {
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uint32_t clk_div;
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uint32_t clk_freq;
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};
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static struct mspm0_clk_cfg mspm0_lfclk_cfg = {
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.clk_freq = DT_PROP(DT_NODELABEL(lfclk), clock_frequency),
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};
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static struct mspm0_clk_cfg mspm0_ulpclk_cfg = {
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.clk_freq = DT_PROP(DT_NODELABEL(ulpclk), clock_frequency),
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.clk_div = MSPM0_ULPCLK_DIV,
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};
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static struct mspm0_clk_cfg mspm0_mclk_cfg = {
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.clk_freq = DT_PROP(DT_NODELABEL(mclk), clock_frequency),
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.clk_div = MSPM0_MCLK_DIV,
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};
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#if MSPM0_MFPCLK_ENABLED
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static struct mspm0_clk_cfg mspm0_mfpclk_cfg = {
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.clk_freq = DT_PROP(DT_NODELABEL(mfpclk), clock_frequency),
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.clk_div = MSPM0_MFPCLK_DIV,
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};
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#endif
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#if MSPM0_PLL_ENABLED
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/* basic checks of the devicetree to follow */
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#if (DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div) && \
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DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk0_div))
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#error "Only CLK2X or CLK0 can be enabled at a time on the PLL"
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#endif
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static DL_SYSCTL_SYSPLLConfig clock_mspm0_cfg_syspll = {
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.inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_32_48_MHZ,
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.sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK2X,
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.sysPLLRef = DL_SYSCTL_SYSPLL_REF_SYSOSC,
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.rDivClk2x = (DT_PROP_OR(DT_NODELABEL(pll), clk2x_div, 1) - 1),
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.rDivClk1 = (DT_PROP_OR(DT_NODELABEL(pll), clk1_div, 1) - 1),
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.rDivClk0 = (DT_PROP_OR(DT_NODELABEL(pll), clk0_div, 1) - 1),
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.qDiv = (DT_PROP(DT_NODELABEL(pll), q_div) - 1),
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.pDiv = CONCAT(DL_SYSCTL_SYSPLL_PDIV_,
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DT_PROP(DT_NODELABEL(pll), p_div)),
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.enableCLK2x = COND_CODE_1(
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DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div),
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(DL_SYSCTL_SYSPLL_CLK2X_ENABLE),
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(DL_SYSCTL_SYSPLL_CLK2X_DISABLE)),
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.enableCLK1 = COND_CODE_1(
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DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk1_div),
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(DL_SYSCTL_SYSPLL_CLK1_ENABLE),
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(DL_SYSCTL_SYSPLL_CLK1_DISABLE)),
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.enableCLK0 = COND_CODE_1(
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DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk0_div),
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(DL_SYSCTL_SYSPLL_CLK0_ENABLE),
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(DL_SYSCTL_SYSPLL_CLK0_DISABLE)),
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};
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#endif
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static int clock_mspm0_on(const struct device *dev, clock_control_subsys_t sys)
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{
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return 0;
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}
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static int clock_mspm0_off(const struct device *dev, clock_control_subsys_t sys)
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{
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return 0;
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}
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static int clock_mspm0_get_rate(const struct device *dev,
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clock_control_subsys_t sys,
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uint32_t *rate)
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{
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struct mspm0_sys_clock *sys_clock = (struct mspm0_sys_clock *)sys;
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switch (sys_clock->clk) {
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case MSPM0_CLOCK_LFCLK:
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*rate = mspm0_lfclk_cfg.clk_freq;
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break;
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case MSPM0_CLOCK_ULPCLK:
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*rate = mspm0_ulpclk_cfg.clk_freq;
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break;
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case MSPM0_CLOCK_MCLK:
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*rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
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break;
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#if MSPM0_MFPCLK_ENABLED
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case MSPM0_CLOCK_MFPCLK:
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*rate = mspm0_mfpclk_cfg.clk_freq;
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break;
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#endif
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case MSPM0_CLOCK_MFCLK:
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case MSPM0_CLOCK_CANCLK:
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int clock_mspm0_init(const struct device *dev)
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{
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/* setup clocks based on specific rates */
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DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
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DL_SYSCTL_setMCLKDivider(mspm0_mclk_cfg.clk_div);
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DL_SYSCTL_setULPCLKDivider(mspm0_ulpclk_cfg.clk_div);
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#if MSPM0_PLL_ENABLED
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#if DT_SAME_NODE(DT_HSCLK_CLOCKS_CTRL, DT_NODELABEL(syspll0))
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clock_mspm0_cfg_syspll.sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK0;
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#endif
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#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(hfclk))
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clock_mspm0_cfg_syspll.sysPLLRef = DL_SYSCTL_SYSPLL_REF_HFCLK;
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#endif
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DL_SYSCTL_configSYSPLL(
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(DL_SYSCTL_SYSPLLConfig *)&clock_mspm0_cfg_syspll);
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#endif
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#if DT_SAME_NODE(DT_HFCLK_CLOCKS_CTRL, DT_NODELABEL(hfxt))
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uint32_t hf_range;
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uint32_t hfxt_freq = DT_PROP(DT_NODELABEL(hfxt),
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clock_frequency) / MHZ(1);
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uint32_t xtal_startup_delay = DT_PROP_OR(DT_NODELABEL(hfxt),
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ti_xtal_startup_delay_us, 0);
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if (hfxt_freq >= 4 &&
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hfxt_freq <= 8) {
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hf_range = DL_SYSCTL_HFXT_RANGE_4_8_MHZ;
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} else if (hfxt_freq > 8 &&
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hfxt_freq <= 16) {
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hf_range = DL_SYSCTL_HFXT_RANGE_8_16_MHZ;
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} else if (hfxt_freq > 16 &&
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hfxt_freq <= 32) {
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hf_range = DL_SYSCTL_HFXT_RANGE_16_32_MHZ;
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} else if (hfxt_freq > 32 &&
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hfxt_freq <= 48) {
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hf_range = DL_SYSCTL_HFXT_RANGE_32_48_MHZ;
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} else {
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return -EINVAL;
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}
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/* startup time in 64us resolution */
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DL_SYSCTL_setHFCLKSourceHFXTParams(hf_range,
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mspm0_hfclk_cfg.xtal_startup_delay / 64,
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true);
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#else
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DL_SYSCTL_setHFCLKSourceHFCLKIN();
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#endif
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#if MSPM0_LFCLK_ENABLED
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#if DT_SAME_NODE(DT_LFCLK_CLOCKS_CTRL, DT_NODELABEL(lfxt))
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DL_SYSCTL_LFCLKConfig config = {0};
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DL_SYSCTL_setLFCLKSourceLFXT(&config);
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#elif DT_SAME_NODE(DT_LFCLK_CLOCKS_CTRL, DT_NODELABEL(lfdig_in))
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DL_SYSCTL_setLFCLKSourceEXLF();
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#endif
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#endif /* MSPM0_LFCLK_ENABLED */
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#if DT_SAME_NODE(DT_MCLK_CLOCKS_CTRL, DT_NODELABEL(hsclk))
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#if DT_SAME_NODE(DT_HSCLK_CLOCKS_CTRL, DT_NODELABEL(hfclk))
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DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK,
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DL_SYSCTL_HSCLK_SOURCE_HFCLK);
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#endif
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#if MSPM0_PLL_ENABLED
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#if (DT_SAME_NODE(DT_HSCLK_CLOCKS_CTRL, DT_NODELABEL(syspll0)) || \
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DT_SAME_NODE(DT_HSCLK_CLOCKS_CTRL, DT_NODELABEL(syspll2x)))
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DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK,
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DL_SYSCTL_HSCLK_SOURCE_SYSPLL);
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#endif
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#endif /* MSPM0_PLL_ENABLED */
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#elif DT_SAME_NODE(DT_MCLK_CLOCKS_CTRL, DT_NODELABEL(lfclk))
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DL_SYSCTL_setMCLKSource(SYSOSC, LFCLK, false);
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#endif /* DT_SAME_NODE(DT_MCLK_CLOCKS_CTRL, DT_NODELABEL(hsclk)) */
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#if MSPM0_MFPCLK_ENABLED
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#if DT_SAME_NODE(DT_MFPCLK_CLOCKS_CTRL, DT_NODELABEL(hfclk))
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DL_SYSCTL_setHFCLKDividerForMFPCLK(mspm0_mfpclk_cfg.clk_div);
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DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_HFCLK);
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#else
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DL_SYSCTL_setMFPCLKSource(DL_SYSCTL_MFPCLK_SOURCE_SYSOSC);
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#endif
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DL_SYSCTL_enableMFPCLK();
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#endif /* MSPM0_MFPCLK_ENABLED */
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return 0;
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}
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static const struct clock_control_driver_api clock_mspm0_driver_api = {
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.on = clock_mspm0_on,
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.off = clock_mspm0_off,
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.get_rate = clock_mspm0_get_rate,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(ckm), &clock_mspm0_init, NULL, NULL, NULL,
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&clock_mspm0_driver_api);

‎dts/bindings/clock/ti,mspm0-clk.yaml

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# Copyright (c) 2025 Texas Instruments Inc.
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# Copyright (c) 2025 Linumiz
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# SPDX-License-Identifier: Apache-2.0
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description: TI MSPM0 Clock
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compatible: "ti,mspm0-clk"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 1
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clocks:
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description: |
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Clock reference source
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clock-frequency:
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type: int
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description: |
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Output clock frequency in Hz.
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clk-div:
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type: int
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description: |
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Clock divider selction value. Valid range [2 ... 16].
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clock-cells:
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- clk

‎dts/bindings/clock/ti,mspm0-osc.yaml

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# Copyright (c) 2025 Texas Instruments Inc.
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# Copyright (c) 2025 Linumiz
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# SPDX-License-Identifier: Apache-2.0
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description: TI MSPM0 oscillator
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compatible: "ti,mspm0-osc"
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include: [fixed-clock.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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ti,xtal-startup-delay-us:
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type: int
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description: |
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Crystal Oscillator startup delay in micro seconds.
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ti,low-cap:
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type: boolean
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description: |
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Specifies if capacitance is less than 3pF to reduce power consumption.

‎dts/bindings/clock/ti,mspm0-pll.yaml

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# Copyright (c) 2024 Texas Instruments Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: TI MSPM0 Phase Locked Loop
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compatible: "ti,mspm0-pll"
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include: [clock-controller.yaml, base.yaml]
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properties:
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clocks:
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required: true
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description: |
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Clock reference source
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"#clock-cells":
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const: 0
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p-div:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 4
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- 8
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description: |
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pdiv is the pre-divider of the output. ref_in / pdiv * qdiv = VCO
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q-div:
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type: int
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required: true
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description: |
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qdiv functions as a multiplier value for the ref_in / pdiv * qdiv = VCO
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Valid Range: 2 - 128
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clk0-div:
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type: int
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description: |
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CLK0 PLL output is only enabled if the divider is present. Use CLK0 on
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the MSPM0 to output to the MCLK, UCLK, and CPUCLK
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Valid Range: 1 - 16
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clk1-div:
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type: int
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description: |
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CLK1 PLL output is only enabled if the divider is present. Use CLK1 on
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the MSPM0 to output to the CANCLK, FCC, or output via EXCLK
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Valid Range: 1 - 16
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clk2x-div:
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type: int
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description: |
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CLK2X PLL output is only enabled if the divider is present. Use CLK2X on
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the MSPM0 to output to the MCLK, UCLK, and CPUCLK instead of CLK0
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Valid Range: 1 - 16

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