dts: arm: nxp: add tpm instances for RT1180

add 6 tpm instances for RT1180
Enable clock for tpm

Signed-off-by: Lucien Zhao <[email protected]>

Author: lucien-nxp

dts/arm/nxp/nxp_rt118x.dtsi

@@ -848,6 +848,60 @@
 			status = "disabled";
 		};
 	};
+
+	tpm1: pwm@4310000 {
+		compatible = "nxp,kinetis-tpm";
+		reg = <0x4310000 0x88>;
+		interrupts = <36 0>;
+		clocks = <&ccm IMX_CCM_TPM1_CLK 0x3b 0>;
+		status = "disabled";
+		#pwm-cells = <3>;
+	};
+
+	tpm2: pwm@4320000 {
+		compatible = "nxp,kinetis-tpm";
+		reg = <0x4320000 0x88>;
+		interrupts = <37 0>;
+		clocks = <&ccm IMX_CCM_TPM2_CLK 0x3c 0>;
+		status = "disabled";
+		#pwm-cells = <3>;
+	};
+
+	tpm3: pwm@24E0000 {
+		compatible = "nxp,kinetis-tpm";
+		reg = <0x24E0000 0x88>;
+		interrupts = <75 0>;
+		clocks = <&ccm IMX_CCM_TPM3_CLK 0x3d 0>;
+		status = "disabled";
+		#pwm-cells = <3>;
+	};
+
+	tpm4: pwm@24F0000 {
+		compatible = "nxp,kinetis-tpm";
+		reg = <0x24F0000 0x88>;
+		interrupts = <76 0>;
+		clocks = <&ccm IMX_CCM_TPM4_CLK 0x3e 0>;
+		status = "disabled";
+		#pwm-cells = <3>;
+	};
+
+	tpm5: pwm@2500000 {
+		compatible = "nxp,kinetis-tpm";
+		reg = <0x2500000 0x88>;
+		interrupts = <77 0>;
+		clocks = <&ccm IMX_CCM_TPM5_CLK 0x3f 0>;
+		status = "disabled";
+		#pwm-cells = <3>;
+	};
+
+	tpm6: pwm@42510000 {
+		compatible = "nxp,kinetis-tpm";
+		reg = <0x42510000 0x88>;
+		interrupts = <78 0>;
+		clocks = <&ccm IMX_CCM_TPM6_CLK 0x40 0>;
+		status = "disabled";
+		#pwm-cells = <3>;
+	};
 };
 
 &flexspi {

soc/nxp/imxrt/imxrt118x/soc.c

@@ -417,6 +417,38 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
 #endif
 
+#ifdef CONFIG_HAS_MCUX_TPM
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(tpm2), okay)
+	/* Configure TPM2 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 3;
+	CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(tpm4), okay)
+	/* Configure TPM4 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 3;
+	CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(tpm5), okay)
+	/* Configure TPM5 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 3;
+	CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(tpm6), okay)
+	/* Configure TPM6 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 3;
+	CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg);
+#endif
+
+#endif /* CONFIG_HAS_MCUX_TPM */
+
 	/* Keep core clock ungated during WFI */
 	CCM->LPCG[1].LPM0 = 0x33333333;
 	CCM->LPCG[1].LPM1 = 0x33333333;