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soc: boards: Add Mediatek MT8186 and MT8188 audio DSPs
These are very similar devices to mt8195, minimal changes needed beyond boilerplate configuration. In the process, this reworks the board/soc layout to be HWMv2 compliant, with "adsp" becoming a CPU cluster beneath the SOC. So the name of the boards to west become e.g. "mt8195/mt8195/adsp" (which can be shortened to "mt8195//adsp" if desired). Note that the cpuclk driver is not yet ported, it works only with 8195 (the clocking/power architecture seems similar between the parts, but the graph of wells and clocks is different and historically these have been three separate drivers in SOF). The biggest changes are in the image/loader scripts, which needed some rework for cross-device portability. Signed-off-by: Andy Ross <[email protected]>
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‎boards/mediatek/mt8186/Kconfig.mt8186

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# Copyright 2024 The ChromiumOS Authors
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MT8186
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select SOC_MT8186

‎boards/mediatek/mt8186/board.yml

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boards:
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- name: mt8186
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vendor: mediatek
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socs:
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- name: mt8186

‎boards/mediatek/mt8186/mt8186_adsp.dts

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/* Copyright 2024 The ChromiumOS Authors
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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sram0: memory@4e100000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x4e100000 DT_SIZE_K(1024)>;
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};
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dram0: memory@60000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x60000000 DT_SIZE_M(16)>;
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};
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dram1: memory@61000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x61000000 DT_SIZE_K(1024)>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0 4>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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intc2: intc@10680010 {
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compatible = "mediatek,adsp_intc";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x10680010 4>;
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status-reg = <0x10680050>;
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interrupts = <2 0 0>;
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mask = <0x3f>;
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interrupt-parent = <&core_intc>;
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};
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ostimer64: ostimer64@10683080 {
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compatible = "mediatek,ostimer64";
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reg = <0x10683080 28>;
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};
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ostimer0: ostimer@10683000 {
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compatible = "mediatek,ostimer";
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reg = <0x10683000 16>;
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interrupt-parent = <&core_intc>;
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interrupts = <18 0 0>;
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};
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mbox0: mbox@10686100 {
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compatible = "mediatek,mbox";
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reg = <0x10686100 16>;
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interrupt-parent = <&intc2>;
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interrupts = <1 0 0>;
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};
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mbox1: mbox@10687100 {
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compatible = "mediatek,mbox";
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reg = <0x10687100 16>;
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interrupt-parent = <&intc2>;
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interrupts = <2 0 0>;
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};
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}; /* soc */
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chosen { };
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aliases { };
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};

‎boards/mediatek/mt8188/Kconfig.mt8188

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# Copyright 2024 The ChromiumOS Authors
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MT8188
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select SOC_MT8188

‎boards/mediatek/mt8188/board.yml

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boards:
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- name: mt8188
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vendor: mediatek
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socs:
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- name: mt8188

‎boards/mediatek/mt8188/mt8188_adsp.dts

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/* Copyright 2024 The ChromiumOS Authors
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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sram0: memory@4e100000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x4e100000 DT_SIZE_K(512)>;
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};
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dram0: memory@60000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x60000000 DT_SIZE_M(15)>;
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};
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dram1: memory@61000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x61000000 DT_SIZE_K(1024)>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0 4>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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intc2: intc@10b80010 {
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compatible = "mediatek,adsp_intc";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x10b80010 4>;
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status-reg = <0x10b80050>;
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interrupts = <2 0 0>;
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mask = <0x3f>;
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interrupt-parent = <&core_intc>;
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};
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ostimer64: ostimer64@10b83080 {
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compatible = "mediatek,ostimer64";
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reg = <0x10b83080 28>;
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};
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ostimer0: ostimer@10b83000 {
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compatible = "mediatek,ostimer";
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reg = <0x10b83000 16>;
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interrupt-parent = <&core_intc>;
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interrupts = <18 0 0>;
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};
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mbox0: mbox@10b86100 {
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compatible = "mediatek,mbox";
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reg = <0x10b86100 16>;
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interrupt-parent = <&intc2>;
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interrupts = <1 0 0>;
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};
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mbox1: mbox@10b87100 {
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compatible = "mediatek,mbox";
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reg = <0x10b87100 16>;
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interrupt-parent = <&intc2>;
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interrupts = <2 0 0>;
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};
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}; /* soc */
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chosen { };
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aliases { };
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};

‎boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp renamed to ‎boards/mediatek/mt8195/Kconfig.mt8195

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# Copyright 2023 The ChromiumOS Authors
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MT8195_ADSP
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select SOC_MT8195_ADSP
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config BOARD_MT8195
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select SOC_MT8195
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help
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Board with Mediatek MT8195 Audio DSP

‎boards/mediatek/mt8195_adsp/board.yml renamed to ‎boards/mediatek/mt8195/board.yml

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boards:
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- name: mt8195_adsp
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- name: mt8195
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full_name: MT8195 ADSP
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vendor: mediatek
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socs:
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- name: mt8195_adsp
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- name: mt8195

‎boards/mediatek/mt8195/mt8195_adsp.dts

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/* Copyright 2023 The ChromiumOS Authors
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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sram0: memory@40000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x40000000 DT_SIZE_K(256)>;
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};
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dram0: memory@60000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x60000000 DT_SIZE_M(17)>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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cpuclk: cpuclk@10000000 {
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compatible = "mediatek,mt8195_cpuclk";
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reg = <0x10000000 380>;
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cg_reg = <0x10720180>;
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pll_ctrl_reg = <0x1000c7e0>;
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freqs_mhz = <26 370 540 720>;
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};
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0 4>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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intc1: intc@10680130 {
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compatible = "mediatek,adsp_intc";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x10680130 4>;
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status-reg = <0x10680150>;
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interrupts = <1 0 0>;
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mask = <0x3ffffff0>;
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interrupt-parent = <&core_intc>;
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};
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intc23: intc@108030f4 {
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compatible = "mediatek,adsp_intc";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x108030f4 4>;
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status-reg = <0x108030fc>;
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interrupts = <23 0 0>;
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mask = <0xffff>;
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interrupt-parent = <&core_intc>;
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};
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ostimer64: ostimer64@1080d080 {
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compatible = "mediatek,ostimer64";
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reg = <0x1080d080 28>;
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};
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ostimer0: ostimer@1080d000 {
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compatible = "mediatek,ostimer";
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reg = <0x1080d000 16>;
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interrupt-parent = <&intc23>;
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interrupts = <11 0 0>;
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};
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mbox0: mbox@10816000 {
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compatible = "mediatek,mbox";
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reg = <0x10816000 56>;
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interrupt-parent = <&intc23>;
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interrupts = <0 0 0>;
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};
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mbox1: mbox@10817000 {
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compatible = "mediatek,mbox";
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reg = <0x10817000 56>;
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interrupt-parent = <&intc23>;
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interrupts = <1 0 0>;
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};
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}; /* soc */
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chosen { };
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aliases { };
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};

‎boards/mediatek/mt8195_adsp/Kconfig.defconfig

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