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Raffael Rostagno
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soc: esp32h2: Add initial support
Add initial support files for ESP32-H2 SoC. Signed-off-by: Raffael Rostagno <[email protected]>
1 parent 49fb053 commit 5437eed

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‎dts/riscv/espressif/esp32h2/esp32h2_common.dtsi

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/interrupt-controller/esp-esp32h2-intmux.h>
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#include <zephyr/dt-bindings/clock/esp32h2_clock.h>
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#include <dt-bindings/pinctrl/esp32h2-pinctrl.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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die-temp0 = &coretemp;
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};
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chosen {
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "espressif,riscv";
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riscv,isa = "rv32imac_zicsr";
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reg = <0>;
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clock-source = <ESP32_CPU_CLK_SRC_PLL>;
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clock-frequency = <DT_FREQ_M(96)>;
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xtal-freq = <DT_FREQ_M(32)>;
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};
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};
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pinctrl: pin-controller {
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compatible = "espressif,esp32-pinctrl";
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status = "okay";
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};
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clock: clock {
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compatible = "espressif,esp32-clock";
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fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
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slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
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#clock-cells = <1>;
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status = "okay";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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sramhp: memory@40800000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x40800000 DT_SIZE_K(320)>;
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zephyr,memory-region = "SRAMHP";
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};
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sramlp: memory@50000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x50000000 DT_SIZE_K(4)>;
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zephyr,memory-region = "SRAMLP";
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};
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intc: interrupt-controller@60010000 {
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compatible = "espressif,esp32-intc";
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x60010000 DT_SIZE_K(4)>;
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status = "okay";
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};
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systimer0: systimer@6000b000 {
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compatible = "espressif,esp32-systimer";
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reg = <0x6000B000 DT_SIZE_K(4)>;
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interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "okay";
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};
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timer0: counter@60009000 {
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compatible = "espressif,esp32-timer";
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reg = <0x60009000 DT_SIZE_K(4)>;
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clocks = <&clock ESP32_TIMG0_MODULE>;
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group = <0>;
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index = <0>;
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interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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counter {
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compatible = "espressif,esp32-counter";
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status = "disabled";
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};
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};
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timer1: counter@6000a000 {
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compatible = "espressif,esp32-timer";
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reg = <0x6000A000 DT_SIZE_K(4)>;
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clocks = <&clock ESP32_TIMG1_MODULE>;
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group = <1>;
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index = <0>;
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interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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counter {
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compatible = "espressif,esp32-counter";
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status = "disabled";
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};
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};
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rtc_timer: rtc_timer@600b0c00 {
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compatible = "espressif,esp32-rtc_timer";
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reg = <0x600B0C00 DT_SIZE_K(1)>;
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clocks = <&clock ESP32_MODULE_MAX>;
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interrupts = <LP_RTC_TIMER_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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trng0: trng@600b2808 {
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compatible = "espressif,esp32-trng";
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reg = <0x600B2808 0x4>;
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clocks = <&clock ESP32_RNG_MODULE>;
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status = "disabled";
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};
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wdt0: watchdog@60009048 {
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compatible = "espressif,esp32-watchdog";
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reg = <0x60009048 0x20>;
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interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&clock ESP32_TIMG0_MODULE>;
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status = "disabled";
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};
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wdt1: watchdog@6000a048 {
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compatible = "espressif,esp32-watchdog";
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reg = <0x6000A048 0x20>;
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interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&clock ESP32_TIMG1_MODULE>;
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status = "disabled";
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};
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flash: flash-controller@60002000 {
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compatible = "espressif,esp32-flash-controller";
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reg = <0x60002000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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erase-block-size = <4096>;
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write-block-size = <4>;
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/* Flash size is specified in SOC/SIP dtsi */
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};
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};
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coretemp: coretemp@6000e058 {
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compatible = "espressif,esp32-temp";
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friendly-name = "coretemp";
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reg = <0x6000E058 0x4>;
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status = "disabled";
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};
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gpio0: gpio@60091000 {
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compatible = "espressif,esp32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x60091000 DT_SIZE_K(4)>;
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interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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ngpios = <32>;
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gpio-reserved-ranges =
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<6 2>, /* GPIO6–7 */
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<15 7>, /* GPIO15–21 */
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<28 4>; /* GPIO28–31 */
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};
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uart0: uart@60000000 {
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compatible = "espressif,esp32-uart";
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reg = <0x60000000 DT_SIZE_K(4)>;
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status = "disabled";
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interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&clock ESP32_UART0_MODULE>;
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};
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uart1: uart@60001000 {
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compatible = "espressif,esp32-uart";
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reg = <0x60001000 DT_SIZE_K(4)>;
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status = "disabled";
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interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&clock ESP32_UART1_MODULE>;
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current-speed = <115200>;
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};
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};
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};

‎dts/riscv/espressif/esp32h2/esp32h2_mini_h2.dtsi

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp32h2_common.dtsi"
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/* 2MB flash */
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&flash0 {
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reg = <0x0 DT_SIZE_M(2)>;
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};

‎dts/riscv/espressif/esp32h2/esp32h2_mini_h4.dtsi

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp32h2_common.dtsi"
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/* 4MB flash */
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&flash0 {
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reg = <0x0 DT_SIZE_M(4)>;
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};

‎dts/riscv/espressif/esp32h2/esp32h2_wroom_02c_h2.dtsi

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp32h2_common.dtsi"
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/* 2MB flash */
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&flash0 {
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reg = <0x0 DT_SIZE_M(2)>;
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};

‎dts/riscv/espressif/esp32h2/esp32h2_wroom_02c_h4.dtsi

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp32h2_common.dtsi"
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/* 4MB flash */
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&flash0 {
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reg = <0x0 DT_SIZE_M(4)>;
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};

‎soc/espressif/common/Kconfig.defconfig

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@@ -1,7 +1,7 @@
1-
# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
33

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if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
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if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 || SOC_SERIES_ESP32H2
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config GEN_ISR_TABLES
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default y if !SOC_ESP32C6_LPCORE
@@ -30,6 +30,7 @@ config XTAL_FREQ_HZ
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 10400000 if XTAL_FREQ_HZ = 26000000
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default 16000000 if XTAL_FREQ_HZ = 32000000
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default 16000000 if XTAL_FREQ_HZ = 40000000
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config SYS_CLOCK_TICKS_PER_SEC
@@ -51,7 +52,7 @@ config ROM_START_OFFSET
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endif # BOOTLOADER_MCUBOOT
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54-
endif # SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
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endif # SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 || SOC_SERIES_ESP32H2
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if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
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‎soc/espressif/common/Kconfig.esptool

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@@ -81,6 +81,7 @@ config ESPTOOLPY_FLASHMODE
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choice ESPTOOLPY_FLASHFREQ
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prompt "Flash SPI speed"
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default ESPTOOLPY_FLASHFREQ_40M if SOC_SERIES_ESP32
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default ESPTOOLPY_FLASHFREQ_48M if SOC_SERIES_ESP32H2
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default ESPTOOLPY_FLASHFREQ_60M if SOC_SERIES_ESP32C2
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default ESPTOOLPY_FLASHFREQ_80M if ESPTOOLPY_FLASHFREQ_80M_DEFAULT
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@@ -102,6 +103,8 @@ config ESPTOOLPY_FLASHFREQ_80M
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bool "80 MHz"
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config ESPTOOLPY_FLASHFREQ_60M
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bool "60 MHz"
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config ESPTOOLPY_FLASHFREQ_48M
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bool "48 MHz"
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config ESPTOOLPY_FLASHFREQ_40M
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bool "40 MHz"
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config ESPTOOLPY_FLASHFREQ_26M
@@ -125,6 +128,7 @@ config ESPTOOLPY_FLASHFREQ
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default '80m' if ESPTOOLPY_FLASHFREQ_120M
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default '80m' if ESPTOOLPY_FLASHFREQ_80M
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default '60m' if ESPTOOLPY_FLASHFREQ_60M
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default '48m' if ESPTOOLPY_FLASHFREQ_48M
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default '40m' if ESPTOOLPY_FLASHFREQ_40M
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default '26m' if ESPTOOLPY_FLASHFREQ_26M
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default '20m' if ESPTOOLPY_FLASHFREQ_20M

‎soc/espressif/common/Kconfig.flash

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@@ -94,7 +94,7 @@ config BOOTLOADER_FLASH_XMC_SUPPORT
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choice BOOTLOADER_VDDSDIO_BOOST
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bool "VDDSDIO LDO voltage"
9696
default BOOTLOADER_VDDSDIO_BOOST_1_9V
97-
depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
97+
depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6 && !SOC_SERIES_ESP32H2
9898
help
9999
If this option is enabled, and VDDSDIO LDO is set to 1.8V (using eFuse
100100
or MTDI bootstrapping pin), bootloader will change LDO settings to

‎soc/espressif/esp32h2/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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vectors.S
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soc_irq.S
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soc.c
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../common/loader.c
8+
)
9+
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zephyr_include_directories(.)
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12+
zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)

‎soc/espressif/esp32h2/Kconfig

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# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_ESP32H2
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select RISCV
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select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
7+
select DYNAMIC_INTERRUPTS
8+
select CLOCK_CONTROL
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select PINCTRL
10+
select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select HAS_ESPRESSIF_HAL

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