board: gd32e103_eval fix device tree errors

Author: feilongfl

boards/arm/gd32e103v_eval/gd32e103v_eval.dts

@@ -73,9 +73,9 @@
 		#size-cells = <1>;
 
 		/* Set 2Kb of storage at the end of the 128Kb of flash */
-		storage_partition: partition@1f800 {
+		storage_partition: partition@801f800 {
 			label = "storage";
-			reg = <0x0001f800 0x00000800>;
+			reg = <0x0801f800 0x00000800>;
 		};
 	};
 };

dts/arm/gigadevice/e1/gd32e1.dtsi

@@ -23,7 +23,7 @@
 		#size-cells = <0>;
 
 		cpu@0 {
-			device_type = "cpu";
+			// device_type = "cpu";
 			compatible = "arm,cortex-m4f";
 			reg = <0>;
 		};
@@ -127,7 +127,7 @@
 				write-block-size = <8>;
 				erase-block-size = <2048>;
 				/* maximum erase time(ms) for a 2K sector */
-				max-erase-time = <25>;
+				// max-erase-time = <25>;
 			};
 		};
 
@@ -139,8 +139,8 @@
 
 		exti: interrupt-controller@40010400 {
 			compatible = "st,stm32-exti";
-			interrupt-controller;
-			#interrupt-cells = <1>;
+			// interrupt-controller;
+			// #interrupt-cells = <1>;
 			reg = <0x40010400 0x400>;
 		};
 
@@ -363,9 +363,9 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				reg = <0x40006400 0x400>, <0x4000A400 0x350>;
-				reg-names = "m_can", "message_ram";
-				interrupts = <21 0>, <22 0>;
-				interrupt-names = "LINE_0", "LINE_1";
+				// reg-names = "m_can", "message_ram";
+				// interrupts = <21 0>, <22 0>;
+				// interrupt-names = "LINE_0", "LINE_1";
 				status = "disabled";
 				label = "CAN_1";
 			};
@@ -585,7 +585,8 @@
 
 		dma1: dma@40020000 {
 			compatible = "st,stm32-dma-v2";
-			#dma-cells = <4>;
+			#dma-cells = <3>;
+			interrupts = <20 0>, <19 0>;
 			reg = <0x40020000 0x400>;
 			clocks = <&rcc GD32_CLOCK_BUS_AHB1 0x1>;
 			dma-offset = <0>;
@@ -595,16 +596,17 @@
 
 		dma2: dma@40020400 {
 			compatible = "st,stm32-dma-v2";
-			#dma-cells = <4>;
+			#dma-cells = <3>;
 			reg = <0x40020400 0x400>;
+			interrupts = <20 0>, <19 0>;
 			clocks = <&rcc GD32_CLOCK_BUS_AHB1 0x2>;
 			status = "disabled";
 			label = "DMA_2";
 		};
 
 		dmamux1: dmamux@40020800 {
 			compatible = "st,stm32-dmamux";
-			#dma-cells = <4>;
+			#dma-cells = <3>;
 			reg = <0x40020800 0x400>;
 			interrupts = <94 0>;
 			clocks = <&rcc GD32_CLOCK_BUS_AHB1 0x4>;