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Mikkel Jakobsencfriedt
Mikkel Jakobsen
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cfriedt
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boards: mimxrt1024_evk: enable mcux ethernet driver and pins
Enables the mcux ethernet driver and pin muxes on the mimxrt1024_evk board in the same way as is done on the mimxrt1020_evk and mimxrt1050_evk. Documentation updated accordingly. Signed-off-by: Mikkel Jakobsen <[email protected]>
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‎boards/arm/mimxrt1024_evk/Kconfig.defconfig‎

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@@ -18,4 +18,11 @@ config FLASH_MCUX_FLEXSPI_NOR
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config FLASH_MCUX_FLEXSPI_XIP
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default y if FLASH
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if NETWORKING
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config NET_L2_ETHERNET
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default y
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endif # NETWORKING
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endif # BOARD_MIMXRT1024_EVK

‎boards/arm/mimxrt1024_evk/doc/index.rst‎

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@@ -79,6 +79,8 @@ features:
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| UART | on-chip | serial port-polling; |
8080
| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| ENET | on-chip | ethernet |
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+-----------+------------+-------------------------------------+
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The default configuration can be found in the defconfig file:
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``boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig``
@@ -101,6 +103,30 @@ The MIMXRT1024 SoC has five pairs of pinmux/gpio controllers.
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+---------------+-----------------+---------------------------+
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| WAKEUP | GPIO | SW4 |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_04 | ENET_RST | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_08 | ENET_REF_CLK | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_09 | ENET_RX_DATA01 | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_10 | ENET_RX_DATA00 | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_11 | ENET_RX_EN | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_12 | ENET_RX_ER | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_13 | ENET_TX_EN | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_14 | ENET_TX_DATA00 | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_15 | ENET_TX_DATA01 | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B1_06 | ENET_INT | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_EMC_41 | ENET_MDC | Ethernet |
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+---------------+-----------------+---------------------------+
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| GPIO_EMC_40 | ENET_MDIO | Ethernet |
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+---------------+-----------------+---------------------------+
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System Clock
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============

‎boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts‎

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@@ -80,6 +80,13 @@
8080
};
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};
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&enet {
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status = "okay";
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ptp {
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status = "okay";
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};
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};
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&lpuart1 {
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status = "okay";
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current-speed = <115200>;

‎boards/arm/mimxrt1024_evk/pinmux.c‎

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@@ -8,6 +8,13 @@
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#include <fsl_iomuxc.h>
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#include <fsl_gpio.h>
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
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static gpio_pin_config_t enet_gpio_config = {
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.direction = kGPIO_DigitalOutput,
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.outputLogic = 0,
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.interruptMode = kGPIO_NoIntmode
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};
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#endif
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static int mimxrt1024_evk_init(const struct device *dev)
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{
@@ -43,7 +50,59 @@ static int mimxrt1024_evk_init(const struct device *dev)
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0xB0A9u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0xB0A9u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 0x31);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDC, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0xB829);
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IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
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/* Initialize ENET_INT GPIO */
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GPIO_PinInit(GPIO1, 4, &enet_gpio_config);
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GPIO_PinInit(GPIO1, 22, &enet_gpio_config);
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/* pull up the ENET_INT before RESET. */
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GPIO_WritePinOutput(GPIO1, 22, 1);
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GPIO_WritePinOutput(GPIO1, 4, 0);
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#endif
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return 0;
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}
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
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static int mimxrt1024_evk_phy_reset(const struct device *dev)
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{
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/* RESET PHY chip. */
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k_busy_wait(USEC_PER_MSEC * 10U);
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GPIO_WritePinOutput(GPIO1, 4, 1);
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return 0;
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}
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#endif
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SYS_INIT(mimxrt1024_evk_init, PRE_KERNEL_1, 0);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
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SYS_INIT(mimxrt1024_evk_phy_reset, PRE_KERNEL_2, 1);
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#endif

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