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dts: bindings: gd32-dma: add config cell property
Add config cell property to gd,gd32-dma. For supporting hardware variation, Splitting base definition to gd,gd32-dma-base.yaml. Signed-off-by: TOKITA Hiroshi <[email protected]>
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-23
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10 files changed

+157
-23
lines changed

‎dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -472,7 +472,7 @@
472472
<15 0>, <16 0>, <17 0>;
473473
clocks = <&cctl GD32_CLOCK_DMA0>;
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dma-channels = <7>;
475-
#dma-cells = <1>;
475+
#dma-cells = <2>;
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status = "disabled";
477477
};
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@@ -483,7 +483,7 @@
483483
<60 0>;
484484
clocks = <&cctl GD32_CLOCK_DMA1>;
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dma-channels = <5>;
486-
#dma-cells = <1>;
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#dma-cells = <2>;
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status = "disabled";
488488
};
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‎dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -411,7 +411,7 @@
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<15 0>, <16 0>, <17 0>;
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clocks = <&cctl GD32_CLOCK_DMA0>;
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dma-channels = <7>;
414-
#dma-cells = <1>;
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#dma-cells = <2>;
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status = "disabled";
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};
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@@ -422,7 +422,7 @@
422422
<60 0>;
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clocks = <&cctl GD32_CLOCK_DMA1>;
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dma-channels = <5>;
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#dma-cells = <1>;
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#dma-cells = <2>;
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status = "disabled";
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};
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};

‎dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@
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interrupts = <9 0>, <10 0>, <11 0>, <48 0>;
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clocks = <&cctl GD32_CLOCK_DMA>;
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dma-channels = <7>;
100-
#dma-cells = <1>;
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#dma-cells = <2>;
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status = "disabled";
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};
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‎dts/arm/gigadevice/gd32f403/gd32f403.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -496,7 +496,7 @@
496496
<15 0>, <16 0>, <17 0>;
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clocks = <&cctl GD32_CLOCK_DMA0>;
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dma-channels = <7>;
499-
#dma-cells = <1>;
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#dma-cells = <2>;
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status = "disabled";
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};
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@@ -507,7 +507,7 @@
507507
<60 0>;
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clocks = <&cctl GD32_CLOCK_DMA1>;
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dma-channels = <5>;
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#dma-cells = <1>;
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#dma-cells = <2>;
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status = "disabled";
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};
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};

‎dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -625,7 +625,7 @@
625625
clocks = <&cctl GD32_CLOCK_DMA0>;
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resets = <&rctl GD32_RESET_DMA0>;
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dma-channels = <8>;
628-
#dma-cells = <1>;
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#dma-cells = <2>;
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status = "disabled";
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};
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@@ -637,7 +637,7 @@
637637
clocks = <&cctl GD32_CLOCK_DMA1>;
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resets = <&rctl GD32_RESET_DMA1>;
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dma-channels = <8>;
640-
#dma-cells = <1>;
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#dma-cells = <2>;
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status = "disabled";
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};
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};

‎dts/bindings/dma/gd,gd32-dma-base.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
# Copyright (c) 2022, TOKITA Hiroshi <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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include: dma-controller.yaml
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properties:
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reg:
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required: true
9+
10+
interrupts:
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required: true
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13+
dma-channels:
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required: true
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clocks:
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required: true

‎dts/bindings/dma/gd,gd32-dma.yaml‎

Lines changed: 59 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4,25 +4,72 @@
44
description: |
55
GD32 DMA controller
66
7-
compatible: "gd,gd32-dma"
7+
channel: Select channel for data transmitting
88
9-
include: [dma-controller.yaml, reset-device.yaml]
9+
config: A 32bit mask specifying the DMA channel configuration
10+
- bit 6-7: Direction (see dma.h)
11+
- 0x0: MEMORY to MEMORY
12+
- 0x1: MEMORY to PERIPH
13+
- 0x2: PERIPH to MEMORY
14+
- 0x3: reserved for PERIPH to PERIPH
1015
11-
properties:
12-
reg:
13-
required: true
16+
- bit 9: Peripheral address increase
17+
- 0x0: no address increment between transfers
18+
- 0x1: increment address between transfers
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20+
- bit 10: Memory address increase
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- 0x0: no address increase between transfers
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- 0x1: increase address between transfers
23+
24+
- bit 11-12: Peripheral data width
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- 0x0: 8 bits
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- 0x1: 16 bits
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- 0x2: 32 bits
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- 0x3: reserved
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- bit 13-14: Memory data width
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- 0x0: 8 bits
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- 0x1: 16 bits
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- 0x2: 32 bits
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- 0x3: reserved
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36+
- bit 15: Peripheral Increment Offset Size
37+
- 0x0: offset size is linked to the peripheral bus width
38+
- 0x1: offset size is fixed to 4 (32-bit alignment)
1439
15-
interrupts:
16-
required: true
40+
- bit 16-17: Priority
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- 0x0: low
42+
- 0x1: medium
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- 0x2: high
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- 0x3: very high
1745
18-
dma-channels:
19-
required: true
46+
Example of devicetree configuration
2047
21-
clocks:
22-
required: true
48+
&spi0 {
49+
status = "okay";
50+
pinctrl-0 = <&spi0_default>;
51+
pinctrl-names = "default";
52+
cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
2353
54+
dmas = <&dma0 3 0>, <&dma0 5 GD32_DMA_PRIORITY_HIGH>;
55+
dma-names = "rx", "tx";
56+
};
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"spi0" uses dma0 for transmitting and receiving in the example.
59+
Each is named "rx" and "tx".
60+
The channel cell assigns channel 3 to receive and channel 5 to transmit.
61+
The config cell can take various configs.
62+
But the setting used depends on each driver implementation.
63+
Set the priority for the transmitting channel as HIGH, LOW(the default) for receive channel.
64+
65+
compatible: "gd,gd32-dma"
66+
67+
include: [ "gd,gd32-dma-base.yaml" ]
68+
69+
properties:
2470
"#dma-cells":
25-
const: 1
71+
const: 2
2672

2773
dma-cells:
2874
- channel
75+
- config

‎dts/riscv/gigadevice/gd32vf103.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -392,7 +392,7 @@
392392
<34 0>, <35 0>, <36 0>;
393393
clocks = <&cctl GD32_CLOCK_DMA0>;
394394
dma-channels = <7>;
395-
#dma-cells = <1>;
395+
#dma-cells = <2>;
396396
status = "disabled";
397397
};
398398

@@ -403,7 +403,7 @@
403403
<79 0>;
404404
clocks = <&cctl GD32_CLOCK_DMA0>;
405405
dma-channels = <5>;
406-
#dma-cells = <1>;
406+
#dma-cells = <2>;
407407
status = "disabled";
408408
};
409409
};

‎include/zephyr/drivers/dma/dma_gd32.h‎

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@@ -0,0 +1,20 @@
1+
/*
2+
* Copyright (c) 2022 TOKITA Hiroshi <[email protected]>
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_GD32_H_
8+
#define ZEPHYR_INCLUDE_DRIVERS_DMA_GD32_H_
9+
10+
#define GD32_DMA_CONFIG_DIRECTION(config) ((config >> 6) & 0x3)
11+
#define GD32_DMA_CONFIG_PERIPH_ADDR_INC(config) ((config >> 9) & 0x1)
12+
#define GD32_DMA_CONFIG_MEMORY_ADDR_INC(config) ((config >> 10) & 0x1)
13+
#define GD32_DMA_CONFIG_PERIPH_WIDTH(config) ((config >> 11) & 0x3)
14+
#define GD32_DMA_CONFIG_MEMORY_WIDTH(config) ((config >> 13) & 0x3)
15+
#define GD32_DMA_CONFIG_PERIPHERAL_INC_FIXED(config) ((config >> 15) & 0x1)
16+
#define GD32_DMA_CONFIG_PRIORITY(config) ((config >> 16) & 0x3)
17+
18+
#define GD32_DMA_FEATURES_FIFO_THRESHOLD(threshold) (threshold & 0x3)
19+
20+
#endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_GD32_H_ */

‎include/zephyr/dt-bindings/dma/gd32_dma.h‎

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@@ -0,0 +1,50 @@
1+
/*
2+
* Copyright (c) 2022 TOKITA Hiroshi <[email protected]>
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GD32_DMA_H_
8+
#define ZEPHYR_INCLUDE_DT_BINDINGS_GD32_DMA_H_
9+
10+
/* macros for channel-cfg */
11+
12+
/* direction defined on bits 6-7 */
13+
#define GD32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6)
14+
#define GD32_DMA_MEMORY_TO_MEMORY GD32_DMA_CH_CFG_DIRECTION(0)
15+
#define GD32_DMA_MEMORY_TO_PERIPH GD32_DMA_CH_CFG_DIRECTION(1)
16+
#define GD32_DMA_PERIPH_TO_MEMORY GD32_DMA_CH_CFG_DIRECTION(2)
17+
18+
/* periph increase defined on bit 9 as true/false */
19+
#define GD32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9)
20+
#define GD32_DMA_NO_PERIPH_ADDR_INC GD32_DMA_CH_CFG_PERIPH_ADDR_INC(0)
21+
#define GD32_DMA_PERIPH_ADDR_INC GD32_DMA_CH_CFG_PERIPH_ADDR_INC(1)
22+
23+
/* memory increase defined on bit 10 as true/false */
24+
#define GD32_DMA_CH_CFG_MEMORY_ADDR_INC(val) ((val & 0x1) << 10)
25+
#define GD32_DMA_NO_MEMORY_ADDR_INC GD32_DMA_CH_CFG_MEMORY_ADDR_INC(0)
26+
#define GD32_DMA_MEMORY_ADDR_INC GD32_DMA_CH_CFG_MEMORY_ADDR_INC(1)
27+
28+
/* periph data size defined on bits 11-12 */
29+
#define GD32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11)
30+
#define GD32_DMA_PERIPH_WIDTH_8BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
31+
#define GD32_DMA_PERIPH_WIDTH_16BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(1)
32+
#define GD32_DMA_PERIPH_WIDTH_32BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(2)
33+
34+
/* memory data size defined on bits 13-14 */
35+
#define GD32_DMA_CH_CFG_MEMORY_WIDTH(val) ((val & 0x3) << 13)
36+
#define GD32_DMA_MEMORY_WIDTH_8BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(0)
37+
#define GD32_DMA_MEMORY_WIDTH_16BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(1)
38+
#define GD32_DMA_MEMORY_WIDTH_32BIT GD32_DMA_CH_CFG_PERIPH_WIDTH(2)
39+
40+
/* priority increment offset defined on bit 15 */
41+
#define GD32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15)
42+
43+
/* priority defined on bits 16-17 as 0, 1, 2, 3 */
44+
#define GD32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16)
45+
#define GD32_DMA_PRIORITY_LOW GD32_DMA_CH_CFG_PRIORITY(0)
46+
#define GD32_DMA_PRIORITY_MEDIUM GD32_DMA_CH_CFG_PRIORITY(1)
47+
#define GD32_DMA_PRIORITY_HIGH GD32_DMA_CH_CFG_PRIORITY(2)
48+
#define GD32_DMA_PRIORITY_VERY_HIGH GD32_DMA_CH_CFG_PRIORITY(3)
49+
50+
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GD32_DMA_H_ */

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