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ARC: nSIM: Add RMX100 platform
This PR adds support for new Synopsys nSIM RMX100 platform. New platform based on RISC-V ISA instead of classic ARC. Signed-off-by: Nikolay Agishev <[email protected]>
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‎boards/snps/nsim/arc_v/Kconfig.defconfig‎

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# Copyright (c) 2024 Synopsys, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_NSIM_ARC_V_RMX100
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config SYS_CLOCK_TICKS_PER_SEC
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default 1000
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 5000000
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endif # BOARD_NSIM_ARC_V_RMX100

‎boards/snps/nsim/arc_v/Kconfig.nsim_arc_v‎

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# Copyright (c) 2024 Synopsys, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NSIM_ARC_V
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select SOC_RMX100 if BOARD_NSIM_ARC_V_RMX100

‎boards/snps/nsim/arc_v/board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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set(SUPPORTED_EMU_PLATFORMS nsim)
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string(SUBSTRING "${BOARD_QUALIFIERS}" 1 -1 NSIM_BASE_FILENAME)
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string(REPLACE "/" "_" NSIM_BASE_FILENAME "${NSIM_BASE_FILENAME}")
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board_set_flasher_ifnset(arc-nsim)
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board_set_debugger_ifnset(arc-nsim)
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set(NSIM_PROPS "${NSIM_BASE_FILENAME}.props")
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board_runner_args(arc-nsim "--props=${NSIM_PROPS}")
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board_finalize_runner_args(arc-nsim)
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include(${ZEPHYR_BASE}/boards/common/mdb-nsim.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake)

‎boards/snps/nsim/arc_v/board.yml‎

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board:
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name: nsim_arc_v
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vendor: snps
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socs:
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- name: rmx100

‎boards/snps/nsim/arc_v/doc/index.rst‎

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.. _nsim_arc_v:
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DesignWare RISC-V nSIM and HAPS FPGA boards
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###########################################
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Overview
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********
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This platform can be used to run Zephyr RTOS on the widest possible range of Synopsys RISC-V processors in
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simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The
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platform includes the following features:
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* RISC-V processor core, which implements riscv32 ISA
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* Virtual serial console (a standard ``ns16550`` UART model)
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Supported board targets for that platform are listed below:
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* ``nsim_arc_v/rmx100`` - Synopsys RISC-V RMX100 core
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.. _board_nsim_arc_v_prop_files:
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It is recommended to look at precise description of a particular board target in ``.props``
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files in :zephyr_file:`boards/snps/nsim_arc_v/support/` directory to understand
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which options are configured and so will be used on invocation of the simulator.
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.. warning::
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All nSIM targets are used for demo and testing purposes. They are not meant to
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represent any real system and so might be renamed, removed or modified at any point.
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Programming and Debugging
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*************************
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Required Hardware and Software
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==============================
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To run single-core Zephyr RTOS applications in simulation on this board,
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either `DesignWare ARC nSIM`_ or `DesignWare ARC Free nSIM`_ is required.
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Building & Running Sample Applications
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======================================
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Most board targets support building with GNU toolchains, however
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there might be exceptions from that, especially for newly added targets. You can check supported
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toolchains for the board targets in the corresponding ``.yaml`` file.
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I.e. for the ``nsim_arc_v/rmx100`` board we can check :zephyr_file:`boards/snps/nsim_arc_v/nsim_arc_v_rmx100.yaml`
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The supported toolchains are listed in ``toolchain:`` array in ``.yaml`` file, where we can find:
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* **zephyr** - implies RISC-V GNU toolchain from Zephyr SDK. You can find more information about
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Zephyr SDK :ref:`here <toolchain_zephyr_sdk>`.
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* **cross-compile** - implies RISC-V GNU cross toolchain, which is not a part of Zephyr SDK. Note that
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some (especially new) board targets may declare ``cross-compile`` toolchain support without
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``zephyr`` toolchain support because corresponding target CPU support hasn't been added to Zephyr
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SDK yet. You can find more information about its usage here: :ref:`here <other_x_compilers>`.
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* **arcmwdt** - implies proprietary ARC MWDT toolchain. You can find more information about its
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usage here: :ref:`here <toolchain_designware_arc_mwdt>`. Not yet supported: work in progress.
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Use this configuration to run basic Zephyr applications and kernel tests in
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nSIM, for example, with the :zephyr:code-sample:`synchronization` sample:
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.. zephyr-app-commands::
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:zephyr-app: samples/synchronization
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:host-os: unix
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:board: nsim_arc_v/rmx100
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:goals: flash
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This will build an image with the synchronization sample app, boot it using
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nSIM, and display the following console output:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-v3.2.0-3948-gd351a024dc87 ***
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thread_a: Hello World from cpu 0 on nsim_arc_v!
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thread_b: Hello World from cpu 0 on nsim_arc_v!
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thread_a: Hello World from cpu 0 on nsim_arc_v!
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thread_b: Hello World from cpu 0 on nsim_arc_v!
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thread_a: Hello World from cpu 0 on nsim_arc_v!
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.. note::
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To exit the simulator, use :kbd:`Ctrl+]`, then :kbd:`Ctrl+c`
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.. _board_nsim_arc_v_verbose_build:
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.. tip::
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You can get more details about the building process by running build in verbose mode. It can be
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done by passing ``-v`` flag to the west: ``west -v build -b nsim_hs samples/synchronization``
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Debugging
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=========
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.. _board_nsim_arc_v_debugging_gdb:
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Debugging with GDB
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------------------
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.. note::
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Debugging on nSIM via GDB is only supported on single-core targets (which use standalone
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nSIM).
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.. note::
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The normal ``west debug`` command won't work for debugging applications using nsim boards
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because both the nSIM simulator and the debugger use the same console for
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input / output.
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In case of GDB debugger it's possible to use a separate terminal windows for GDB and nSIM to
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avoid intermixing their output.
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After building your application, open two terminal windows. In terminal one, use nSIM to start a GDB
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server and wait for a remote connection with following command:
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.. code-block:: console
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west debugserver --runner arc-nsim
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In terminal two, connect to the GDB server using RISC-V GDB. You can find it in Zephyr SDK:
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* you should use :file:`riscv64-zephyr-elf-gdb`
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This command loads the symbol table from the elf binary file, for example the
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:file:`build/zephyr/zephyr.elf` file:
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.. code-block:: console
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riscv64-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf
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Now the debug environment has been set up, and it's possible to debug the application with gdb
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commands.
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Modifying the configuration
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***************************
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If modification of existing nsim configuration is required or even there's a need in creation of a
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new one it's required to maintain alignment between
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* Zephyr OS configuration
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* nSIM configuration
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* GNU toolchain compiler options
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.. note::
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The ``.tcf`` configuration files are not supported by Zephyr directly. There are multiple
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reasons for that. ``.tcf`` perfectly suits building of bare-metal single-thread application -
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in that case all the compiler options from ``.tcf`` are passed to the compiler, so all the HW
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features are used by the application and optimal code is being generated.
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The situation is completely different when multi-thread feature-rich operation system is
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considered. Of course it is still possible to build all the code with all the
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options from ``.tcf`` - but that may be far from optimal solution. For example, such approach
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require so save & restore full register context for all tasks (and sometimes even for
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interrupts). And for DSP-enabled or for FPU-enabled systems that leads to dozens of extra
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registers save and restore even if the most of the user and kernel tasks don't actually use
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DSP or FPU. Instead we prefer to fine-tune the HW features usage which (with all its pros)
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require us to maintain them separately from ``.tcf`` configuration.
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Zephyr OS configuration
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=======================
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Zephyr OS configuration is defined via Kconfig and Device tree. These are non RISC-V-specific
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mechanisms which are described in :ref:`board porting guide <board_porting_guide>`.
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It is advised to look for ``<board_name>_defconfig``, ``<board_name>.dts`` and
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``<board_name>.yaml`` as an entry point for board target.
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nSIM configuration
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==================
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nSIM configuration is defined in :ref:`props files <board_nsim_arc_v_prop_files>`.
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Generally they are identical to the values from corresponding ``.tcf`` configuration with few
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exceptions:
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* The UART model is added
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* CLINT model is added
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GNU toolchain compiler options
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=====================================
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The hardware-specific compiler options are set in corresponding SoC cmake file. For ``nsim_arc_v`` board
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it is :zephyr_file:`soc/snps/nsim/arc_v/CMakeLists.txt`.
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For the GNU toolchain the basic configuration is set via ``-march`` which is defined in generic code
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and based on the selected CPU model via Kconfig. It still can be forcefully set to required value
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on SoC level.
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.. note::
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The non hardware-specific compiler options like optimizations, library selections, C / C++
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language options are still set in Zephyr generic code. It could be observed by
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:ref:`running build in verbose mode <board_nsim_arc_v_verbose_build>`.
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References
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**********
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.. _Designware ARC nSIM: https://www.synopsys.com/dw/ipdir.php?ds=sim_nsim
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.. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi
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.. _HAPS: https://www.synopsys.com/verification/prototyping/haps.html
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.. _ARC MWDT: https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware

‎boards/snps/nsim/arc_v/nsim_arc_v_rmx100.dts‎

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/dts-v1/;
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#include "rmx100.dtsi"
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/ {
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model = "Synopsys RMX100";
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compatible = "snps,rmx100";
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aliases {
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uart-0 = &uart0;
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};
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chosen {
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zephyr,sram = &ddr0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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};

‎boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml‎

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identifier: nsim_arc_v/rmx100
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name: Synopsys rmx100
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simulation: nsim
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simulation_exec: nsimdrv
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type: sim
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arch: riscv
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toolchain:
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- zephyr
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- cross-compile
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testing:
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ignore_tags:
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- net
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- bluetooth
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vendor: snps

‎boards/snps/nsim/arc_v/nsim_arc_v_rmx100_defconfig‎

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# Copyright (c) 2024 Synopsys, Inc.
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_XIP=n
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_BUILD_OUTPUT_HEX=y
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CONFIG_INCLUDE_RESET_VECTOR=y
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CONFIG_LOG=y

‎boards/snps/nsim/arc_v/rmx100.dtsi‎

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#include "rmx1xx.dtsi"
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/ {
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ddr0: memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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};

‎boards/snps/nsim/arc_v/rmx1xx.dtsi‎

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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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timebase-frequency = <5000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "snps,av5rmx", "riscv";
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device_type = "cpu";
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reg = <0>;
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clock-frequency = <5000000>;
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riscv,isa = "rv32imac_zicsr_zifencei";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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ranges;
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interrupt-parent = <&clint>;
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#address-cells = <1>;
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#size-cells = <1>;
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clint: clint@2000000 {
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compatible = "sifive,clint0";
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reg = <0x2000000 0x1000>;
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7>;
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interrupt-names = "soft0", "timer0";
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};
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uart0: serial@10000000{
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compatible = "ns16550", "snps,dw-apb-uart";
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reg = <0x10000000 0x400>;
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reg-shift = <2>;
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/* AIA interrupt controller is not currently implemented,
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* so connect UART interrupt to 17th line as a stub to
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* make build system and test framework happy.
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*/
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interrupt-parent = <&cpu0_intc>;
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interrupts = <17>;
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clock-frequency = <50000000>;
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status = "disabled";
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};
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};
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};

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