boards: riscv: qemu: enable coverage support for all targets

Support code coverage on all RISC-V qemu targets. Additional
boards may choose to enable coveage support as well.

Tested by following the procedure documented at
https://docs.zephyrproject.org/latest/develop/test/coverage.html
with the qemu_riscv64 target.

Signed-off-by: Christopher Friedt <[email protected]>

Author: Christopher Friedt

boards/riscv/qemu_riscv32/Kconfig.board

@@ -4,6 +4,7 @@ config BOARD_QEMU_RISCV32
 	bool "QEMU RISCV32 target"
 	depends on SOC_RISCV_VIRT
 	select QEMU_TARGET
+	select HAS_COVERAGE_SUPPORT
 	select CPU_HAS_FPU
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_ZICSR
@@ -13,6 +14,7 @@ config BOARD_QEMU_RISCV32_SMP
 	bool "QEMU RISCV32 SMP target"
 	depends on SOC_RISCV_VIRT
 	select QEMU_TARGET
+	select HAS_COVERAGE_SUPPORT
 	select CPU_HAS_FPU
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_ZICSR
@@ -22,6 +24,7 @@ config BOARD_QEMU_RISCV32_XIP
 	bool "QEMU RISCV32 XIP target"
 	depends on SOC_RISCV_SIFIVE_FREEDOM
 	select QEMU_TARGET
+	select HAS_COVERAGE_SUPPORT
 	select CPU_HAS_FPU
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_ZICSR

boards/riscv/qemu_riscv32e/Kconfig.board

@@ -5,6 +5,7 @@ config BOARD_QEMU_RISCV32E
 	bool "QEMU RISCV32E target"
 	depends on SOC_RISCV_VIRT
 	select QEMU_TARGET
+	select HAS_COVERAGE_SUPPORT
 	select RISCV_ISA_RV32E
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI

boards/riscv/qemu_riscv64/Kconfig.board

@@ -6,6 +6,7 @@ config BOARD_QEMU_RISCV64
 	depends on SOC_RISCV_VIRT
 	select QEMU_TARGET
 	select 64BIT
+	select HAS_COVERAGE_SUPPORT
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select RISCV_ISA_RV64I
 	select RISCV_ISA_EXT_ZICSR
@@ -16,6 +17,7 @@ config BOARD_QEMU_RISCV64_SMP
 	depends on SOC_RISCV_VIRT
 	select QEMU_TARGET
 	select 64BIT
+	select HAS_COVERAGE_SUPPORT
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select RISCV_ISA_RV64I
 	select RISCV_ISA_EXT_ZICSR