drivers: mspi: mspi_dw: support newer IP revisions

Bitmask offsets for the MSPI_DW peripheral are incorrect for the
4.03a databook for the DW APB SSI. Add a "v2" compatible to handle these
changed offsets. The compatible does not define new binding properties,
just modifies the register offsets.

Additionally, handle writing the DFS32 mask for v2 of this compatible,
as newer IP supports a dataframe size up to 32 bits.

Signed-off-by: Daniel DeGrasse <[email protected]>

Author: danieldegrasse

drivers/mspi/mspi_dw.c

@@ -820,8 +820,9 @@ static int start_next_packet(const struct device *dev, k_timeout_t timeout)
 	dev_data->dummy_bytes = 0;
 	dev_data->bytes_to_discard = 0;
 
-	dev_data->ctrlr0 &= ~CTRLR0_TMOD_MASK
-			 &  ~CTRLR0_DFS_MASK;
+	dev_data->ctrlr0 &= ~(CTRLR0_TMOD_MASK)
+			  & ~(CTRLR0_DFS_MASK)
+			  & ~(CTRLR0_DFS32_MASK);
 
 	dev_data->spi_ctrlr0 &= ~SPI_CTRLR0_WAIT_CYCLES_MASK;
 
@@ -830,16 +831,20 @@ static int start_next_packet(const struct device *dev, k_timeout_t timeout)
 	     dev_data->xfer.addr_length != 0)) {
 		dev_data->bytes_per_frame_exp = 0;
 		dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS_MASK, 7);
+		dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS32_MASK, 7);
 	} else {
 		if ((packet->num_bytes % 4) == 0) {
 			dev_data->bytes_per_frame_exp = 2;
 			dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS_MASK, 31);
+			dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS32_MASK, 31);
 		} else if ((packet->num_bytes % 2) == 0) {
 			dev_data->bytes_per_frame_exp = 1;
 			dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS_MASK, 15);
+			dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS32_MASK, 15);
 		} else {
 			dev_data->bytes_per_frame_exp = 0;
 			dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS_MASK, 7);
+			dev_data->ctrlr0 |= FIELD_PREP(CTRLR0_DFS32_MASK, 7);
 		}
 	}
 

drivers/mspi/mspi_dw.h

@@ -1,32 +1,42 @@
 /*
  * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Tenstorrent AI ULC
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#if DT_HAS_COMPAT_STATUS_OKAY(snps_designware_ssi_v2)
+/*
+ * Later versions of the SSI have different register offsets. Define a macro
+ * to use these.
+ */
+#define SSI_VERSION_2 1
+#endif
+
 /*
  * This header is part of mspi_dw.c extracted only for clarity.
  * It is not supposed to be included by any file other than mspi_dw.c.
  */
 
 /* CTRLR0 - Control Register 0 */
-#define CTRLR0_SPI_FRF_MASK	GENMASK(23, 22)
+#define CTRLR0_SPI_FRF_MASK	COND_CODE_1(SSI_VERSION_2, GENMASK(22, 21), GENMASK(23, 22))
 #define CTRLR0_SPI_FRF_STANDARD	0UL
 #define CTRLR0_SPI_FRF_DUAL	1UL
 #define CTRLR0_SPI_FRF_QUAD	2UL
 #define CTRLR0_SPI_FRF_OCTAL	3UL
-#define CTRLR0_TMOD_MASK	GENMASK(11, 10)
+#define CTRLR0_TMOD_MASK	COND_CODE_1(SSI_VERSION_2, GENMASK(9, 8), GENMASK(11, 10))
 #define CTRLR0_TMOD_TX_RX	0UL
 #define CTRLR0_TMOD_TX		1UL
 #define CTRLR0_TMOD_RX		2UL
 #define CTRLR0_TMOD_EEPROM	3UL
-#define CTRLR0_SCPOL_BIT	BIT(9)
-#define CTRLR0_SCPH_BIT		BIT(8)
-#define CTRLR0_FRF_MASK		GENMASK(7, 6)
+#define CTRLR0_SCPOL_BIT	COND_CODE_1(SSI_VERSION_2, BIT(7), BIT(9))
+#define CTRLR0_SCPH_BIT		COND_CODE_1(SSI_VERSION_2, BIT(6), BIT(8))
+#define CTRLR0_FRF_MASK		COND_CODE_1(SSI_VERSION_2, GENMASK(5, 4), GENMASK(7, 6))
 #define CTRLR0_FRF_SPI		0UL
 #define CTRLR0_FRF_SSP		1UL
 #define CTRLR0_FRF_MICROWIRE	2UL
-#define CTRLR0_DFS_MASK		GENMASK(4, 0)
+#define CTRLR0_DFS_MASK		COND_CODE_1(SSI_VERSION_2, GENMASK(3, 0), GENMASK(4, 0))
+#define CTRLR0_DFS32_MASK	COND_CODE_1(SSI_VERSION_2, GENMASK(20, 16), (0))
 
 /* CTRLR1- Control Register 1 */
 #define CTRLR1_NDF_MASK		GENMASK(15, 0)