soc: arm: stm32g0 with USB-C PD cannot use CC1 and CC2 pins by default

With this patch, the UCPD1 _CC1 and _CC2 pins
are disabling the USB Type-C and Power Delivery Dead Battery.

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

soc/arm/st_stm32/stm32g0/soc.c

@@ -16,6 +16,10 @@
 #include <arch/arm/aarch32/cortex_m/cmsis.h>
 #include <linker/linker-defs.h>
 #include <string.h>
+#if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
+#include <stm32_ll_system.h>
+#include <stm32_ll_bus.h>
+#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
 
 /**
  * @brief Perform basic hardware initialization at boot.
@@ -44,6 +48,12 @@ static int stm32g0_init(const struct device *arg)
 	/* At reset, system core clock is set to 16 MHz from HSI */
 	SystemCoreClock = 16000000;
 
+#if defined(SYSCFG_CFGR1_UCPD1_STROBE) || defined(SYSCFG_CFGR1_UCPD2_STROBE)
+	/* Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */
+	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
+	LL_SYSCFG_DisableDBATT(LL_SYSCFG_UCPD1_STROBE | LL_SYSCFG_UCPD2_STROBE);
+#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
+
 	return 0;
 }