drivers: display: uc8151d: Add UC8151D display controller support

Add support for the UltraChip UC8151D e-paper display (EPD) controller.
The UC8151D is part of the UC81xx family of display controllers commonly
used in e-ink displays.

This implementation extends the existing UC81xx driver infrastructure by
adding device tree bindings, Kconfig options, and the necessary driver
code to support the UC8151D variant.

Signed-off-by: Marc Espuña <[email protected]>

Author: mespunaiot

drivers/display/Kconfig.uc81xx

@@ -6,7 +6,7 @@
 config UC81XX
 	bool "UltraChip UC81xx compatible display controller driver"
 	default y
-	depends on DT_HAS_ULTRACHIP_UC8175_ENABLED || DT_HAS_ULTRACHIP_UC8176_ENABLED || DT_HAS_ULTRACHIP_UC8179_ENABLED
+	depends on DT_HAS_ULTRACHIP_UC8175_ENABLED || DT_HAS_ULTRACHIP_UC8176_ENABLED || DT_HAS_ULTRACHIP_UC8151D_ENABLED || DT_HAS_ULTRACHIP_UC8179_ENABLED
 	select MIPI_DBI
 	help
 	  Enable driver for UC81xx compatible controller.

drivers/display/uc81xx.c

@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2025 Cactus Engineering S.L
  * Copyright (c) 2022 Andreas Sandberg
  * Copyright (c) 2020 PHYTEC Messtechnik GmbH
  * Copyright 2024 NXP
@@ -65,6 +66,7 @@ struct uc81xx_quirks {
 	uint16_t max_height;
 
 	bool auto_copy;
+	bool pon_after_softstart;
 
 	int (*set_cdi)(const struct device *dev, bool border);
 	int (*set_tres)(const struct device *dev);
@@ -227,6 +229,22 @@ static int uc81xx_set_profile(const struct device *dev,
 			return -EIO;
 		}
 
+		if (config->quirks->pon_after_softstart) {
+			/* UC8151D requires PON command after BTST for proper
+			 * power initialization
+			 */
+			LOG_DBG("Sending PON command after softstart");
+			if (uc81xx_write_cmd(dev, UC81XX_CMD_PON, NULL, 0)) {
+				return -EIO;
+			}
+
+			/* Wait for power stabilization and BUSY_N = HIGH */
+			k_sleep(K_MSEC(UC81XX_PON_DELAY));
+			uc81xx_busy_wait(dev);
+
+			LOG_DBG("PON command completed");
+		}
+
 		/*
 		 * Enable LUT overrides if a LUT has been provided by
 		 * the user.
@@ -660,6 +678,7 @@ static const struct uc81xx_quirks uc8175_quirks = {
 	.max_height = 160,
 
 	.auto_copy = false,
+	.pon_after_softstart = false,
 
 	.set_cdi = uc8176_set_cdi,
 	.set_tres = uc81xx_set_tres_8,
@@ -673,13 +692,92 @@ static const struct uc81xx_quirks uc8176_quirks = {
 	.max_height = 300,
 
 	.auto_copy = false,
+	.pon_after_softstart = false,
 
 	.set_cdi = uc8176_set_cdi,
 	.set_tres = uc81xx_set_tres_16,
 	.set_ptl = uc81xx_set_ptl_16,
 };
 #endif
 
+#if DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8151d)
+static int uc8151d_set_tres(const struct device *dev)
+{
+	const struct uc81xx_config *config = dev->config;
+	/* Pass pixel coordinates directly; hardware interprets as byte+bit encoding
+	 * See UC8151D datasheet page 22 (TRES command, R61h)
+	 */
+	const struct uc8151d_tres tres = {
+		.hres = config->width,
+		.vres = sys_cpu_to_be16(config->height),
+	};
+
+	LOG_HEXDUMP_DBG(&tres, sizeof(tres), "TRES");
+
+	return uc81xx_write_cmd(dev, UC81XX_CMD_TRES,
+			       (const void *)&tres, sizeof(tres));
+}
+
+static int uc8151d_set_ptl(const struct device *dev, uint16_t x, uint16_t y,
+			   uint16_t x_end_idx, uint16_t y_end_idx,
+			   const struct display_buffer_descriptor *desc)
+{
+	/* Pass pixel coordinates directly; hardware interprets as byte+bit encoding
+	 * See UC8151D datasheet page 26 (Partial Window command, R90h)
+	 */
+	const struct uc8151d_ptl ptl = {
+		.hrst = x & BIT_MASK(8),
+		.hred = x_end_idx & BIT_MASK(8),
+		.vrst = sys_cpu_to_be16(y & BIT_MASK(9)),
+		.vred = sys_cpu_to_be16(y_end_idx & BIT_MASK(9)),
+		.pt_scan = UC81XX_PTL_FLAG_PT_SCAN,
+	};
+
+	/* Setup Partial Window and enable Partial Mode */
+	LOG_HEXDUMP_DBG(&ptl, sizeof(ptl), "ptl");
+
+	return uc81xx_write_cmd(dev, UC81XX_CMD_PTL,
+			       (const void *)&ptl, sizeof(ptl));
+}
+
+static int uc8151d_set_cdi(const struct device *dev, bool border)
+{
+	const struct uc81xx_config *config = dev->config;
+	const struct uc81xx_data *data = dev->data;
+	const struct uc81xx_profile *p = config->profiles[data->profile];
+	uint8_t cdi = UC8151D_CDI_DEFAULT;  /* Start with 0xD7 */
+
+	if (!p || !p->override_cdi) {
+		/* Use default CDI value if no profile override */
+		cdi = UC8151D_CDI_DEFAULT;
+	} else {
+		/* Keep VBD and DDX bits from default, use profile CDI interval */
+		cdi = (UC8151D_CDI_DEFAULT & (UC8151D_CDI_VBD_MASK | UC8151D_CDI_DDX_MASK)) |
+		      (p->cdi & UC8151D_CDI_MASK);
+	}
+
+	if (!border) {
+		/* Set VBD to floating for no border */
+		cdi = (cdi & ~UC8151D_CDI_VBD_MASK) | UC8151D_CDI_VBD_FLOATING;
+	}
+
+	LOG_DBG("CDI: %#hhx", cdi);
+	return uc81xx_write_cmd_uint8(dev, UC81XX_CMD_CDI, cdi);
+}
+
+static const struct uc81xx_quirks uc8151d_quirks = {
+	.max_width = 160,      /* Actual max from datasheet */
+	.max_height = 296,     /* Actual max from datasheet */
+
+	.auto_copy = false,    /* Manual copy required */
+	.pon_after_softstart = true,
+
+	.set_cdi = uc8151d_set_cdi,
+	.set_tres = uc8151d_set_tres,
+	.set_ptl = uc8151d_set_ptl,
+};
+#endif
+
 #if DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8179)
 static int uc8179_set_cdi(const struct device *dev, bool border)
 {
@@ -706,6 +804,7 @@ static const struct uc81xx_quirks uc8179_quirks = {
 	.max_height = 600,
 
 	.auto_copy = true,
+	.pon_after_softstart = false,
 
 	.set_cdi = uc8179_set_cdi,
 	.set_tres = uc81xx_set_tres_16,
@@ -813,5 +912,8 @@ DT_FOREACH_STATUS_OKAY_VARGS(ultrachip_uc8175, UC81XX_DEFINE,
 DT_FOREACH_STATUS_OKAY_VARGS(ultrachip_uc8176, UC81XX_DEFINE,
 			     &uc8176_quirks);
 
+DT_FOREACH_STATUS_OKAY_VARGS(ultrachip_uc8151d, UC81XX_DEFINE,
+			     &uc8151d_quirks);
+
 DT_FOREACH_STATUS_OKAY_VARGS(ultrachip_uc8179, UC81XX_DEFINE,
 			     &uc8179_quirks);

drivers/display/uc81xx_regs.h

@@ -140,7 +140,48 @@ struct uc81xx_ptl16 {
 
 BUILD_ASSERT(sizeof(struct uc81xx_ptl16) == 9);
 
-#define UC81XX_PTL_FLAG_PT_SCAN			BIT(0)
+/* UC8151D-specific structures */
+#if DT_HAS_COMPAT_STATUS_OKAY(ultrachip_uc8151d)
+struct uc8151d_tres {
+	/* Horizontal resolution in pixels.
+	 * Hardware interprets as bank[7:3] | column[2:0]
+	 */
+	uint8_t hres;
+	uint16_t vres;       /* Vertical resolution (big-endian) */
+} __packed;
+
+BUILD_ASSERT(sizeof(struct uc8151d_tres) == 3);
+
+struct uc8151d_ptl {
+	uint8_t hrst;        /* Horizontal start (byte-packed) */
+	uint8_t hred;        /* Horizontal end (byte-packed) */
+	uint16_t vrst;       /* Vertical start (big-endian, 9-bit) */
+	uint16_t vred;       /* Vertical end (big-endian, 9-bit) */
+	uint8_t pt_scan;      /* PT_SCAN - Scan mode */
+} __packed;
+
+BUILD_ASSERT(sizeof(struct uc8151d_ptl) == 7);
+
+/* UC8151D CDI register bit fields */
+#define UC8151D_CDI_VBD_MASK		GENMASK(7, 6)
+#define UC8151D_CDI_DDX_MASK		GENMASK(5, 4)
+#define UC8151D_CDI_MASK			GENMASK(3, 0)
+#define UC8151D_CDI_DEFAULT			0xD7    /* Default value */
+
+/* UC8151D CDI VBD values for border control */
+#define UC8151D_CDI_VBD_FLOATING	0x00    /* Floating border */
+#define UC8151D_CDI_VBD_LUT1		0x40    /* LUT1 border */
+#define UC8151D_CDI_VBD_LUT2		0x80    /* LUT2 border */
+#define UC8151D_CDI_VBD_LUT3		0xC0    /* LUT3 border */
+
+/* UC8151D CDI DDX values for data polarity */
+#define UC8151D_CDI_DDX_DEFAULT		0x10    /* Default DDX setting */
+
+/* UC8151D CDI interval values */
+#define UC8151D_CDI_10_HSYNC		0x07    /* 10 hsync (default) */
+#endif
+
+#define UC81XX_PTL_FLAG_PT_SCAN		BIT(0)
 
 /* Time constants in ms */
 #define UC81XX_RESET_DELAY			10U

dts/bindings/display/ultrachip,uc8151d.yaml

@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Cactus Engineering S.L
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  UltraChip UC8151D EPD controller with native 160x296 monochrome (1bpp)
+  display support.
+
+compatible: "ultrachip,uc8151d"
+
+include: ultrachip,uc81xx-common.yaml