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danieldegrassecarlescufi
danieldegrasse
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carlescufi
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drivers: mipi: introduce MCUX MIPI DSI 2L driver
Introduce driver for MCUX MIPI DSI 2L. This IP block differs slightly from the existing MCUX MIPI peripheral, and uses a different hardware abstraction layer. For these reasons, a new driver was introduced rather than extending the existing mcux_dsi implementation. Signed-off-by: Daniel DeGrasse <[email protected]>
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‎drivers/mipi_dsi/CMakeLists.txt

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zephyr_sources_ifdef(CONFIG_MIPI_DSI mipi_dsi.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DSI_MCUX dsi_mcux.c)
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zephyr_sources_ifdef(CONFIG_MIPI_DSI_MCUX_2L dsi_mcux_2l.c)

‎drivers/mipi_dsi/Kconfig.mcux

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# Copyright (c) 2022, NXP
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# Copyright 2022-2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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config MIPI_DSI_MCUX
@@ -7,3 +7,10 @@ config MIPI_DSI_MCUX
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depends on DT_HAS_NXP_IMX_MIPI_DSI_ENABLED
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help
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NXP MIPI DSI controller driver
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config MIPI_DSI_MCUX_2L
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bool "NXP MCUX MIPI-DSI 2L Controller"
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default y
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depends on DT_HAS_NXP_MIPI_DSI_2L_ENABLED
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help
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NXP MIPI DSI 2L controller driver

‎drivers/mipi_dsi/dsi_mcux_2l.c

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/*
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* Copyright 2023, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Based on dsi_mcux.c, which is (c) 2022 NXP */
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#define DT_DRV_COMPAT nxp_mipi_dsi_2l
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/mipi_dsi.h>
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#include <fsl_mipi_dsi.h>
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#include <fsl_clock.h>
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#include <zephyr/logging/log.h>
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#include <soc.h>
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LOG_MODULE_REGISTER(dsi_mcux_host, CONFIG_MIPI_DSI_LOG_LEVEL);
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struct mcux_mipi_dsi_config {
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MIPI_DSI_HOST_Type *base;
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dsi_dpi_config_t dpi_config;
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bool auto_insert_eotp;
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const struct device *bit_clk_dev;
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clock_control_subsys_t bit_clk_subsys;
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const struct device *esc_clk_dev;
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clock_control_subsys_t esc_clk_subsys;
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const struct device *pixel_clk_dev;
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clock_control_subsys_t pixel_clk_subsys;
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uint32_t dphy_ref_freq;
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};
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static int dsi_mcux_attach(const struct device *dev,
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uint8_t channel,
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const struct mipi_dsi_device *mdev)
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{
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const struct mcux_mipi_dsi_config *config = dev->config;
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dsi_dphy_config_t dphy_config;
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dsi_config_t dsi_config;
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uint32_t dphy_bit_clk_freq;
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uint32_t dphy_esc_clk_freq;
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uint32_t dsi_pixel_clk_freq;
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uint32_t bit_width;
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DSI_GetDefaultConfig(&dsi_config);
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dsi_config.numLanes = mdev->data_lanes;
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dsi_config.autoInsertEoTp = config->auto_insert_eotp;
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/* Init the DSI module. */
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DSI_Init(config->base, &dsi_config);
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/* Get the DPHY bit clock frequency */
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if (clock_control_get_rate(config->bit_clk_dev,
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config->bit_clk_subsys,
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&dphy_bit_clk_freq)) {
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return -EINVAL;
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};
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/* Get the DPHY ESC clock frequency */
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if (clock_control_get_rate(config->esc_clk_dev,
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config->esc_clk_subsys,
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&dphy_esc_clk_freq)) {
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return -EINVAL;
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}
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/* Get the Pixel clock frequency */
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if (clock_control_get_rate(config->pixel_clk_dev,
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config->pixel_clk_subsys,
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&dsi_pixel_clk_freq)) {
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return -EINVAL;
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}
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switch (config->dpi_config.pixelPacket) {
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case kDSI_PixelPacket16Bit:
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bit_width = 16;
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break;
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case kDSI_PixelPacket18Bit:
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__fallthrough;
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case kDSI_PixelPacket18BitLoosely:
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bit_width = 18;
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break;
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case kDSI_PixelPacket24Bit:
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bit_width = 24;
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break;
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default:
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return -EINVAL; /* Invalid bit width enum value? */
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}
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/* Init DPHY.
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*
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* The DPHY bit clock must be fast enough to send out the pixels, it should be
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* larger than:
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*
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* (Pixel clock * bit per output pixel) / number of MIPI data lane
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*/
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if (((dsi_pixel_clk_freq * bit_width) / mdev->data_lanes) > dphy_bit_clk_freq) {
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return -EINVAL;
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}
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DSI_GetDphyDefaultConfig(&dphy_config, dphy_bit_clk_freq, dphy_esc_clk_freq);
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if (config->dphy_ref_freq != 0) {
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dphy_bit_clk_freq = DSI_InitDphy(config->base,
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&dphy_config, config->dphy_ref_freq);
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} else {
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/* DPHY PLL is not present, ref clock is unused */
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DSI_InitDphy(config->base, &dphy_config, 0);
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}
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/* Init DPI interface. */
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DSI_SetDpiConfig(config->base, &config->dpi_config, mdev->data_lanes,
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dsi_pixel_clk_freq, dphy_bit_clk_freq);
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imxrt_post_init_display_interface();
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return 0;
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}
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static ssize_t dsi_mcux_transfer(const struct device *dev, uint8_t channel,
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struct mipi_dsi_msg *msg)
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{
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const struct mcux_mipi_dsi_config *config = dev->config;
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dsi_transfer_t dsi_xfer = {0};
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status_t status;
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dsi_xfer.virtualChannel = channel;
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dsi_xfer.txDataSize = msg->tx_len;
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dsi_xfer.txData = msg->tx_buf;
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dsi_xfer.rxDataSize = msg->rx_len;
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dsi_xfer.rxData = msg->rx_buf;
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switch (msg->type) {
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case MIPI_DSI_DCS_READ:
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LOG_ERR("DCS Read not yet implemented or used");
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return -ENOTSUP;
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case MIPI_DSI_DCS_SHORT_WRITE:
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dsi_xfer.sendDscCmd = true;
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dsi_xfer.dscCmd = msg->cmd;
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dsi_xfer.txDataType = kDSI_TxDataDcsShortWrNoParam;
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break;
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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__fallthrough;
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case MIPI_DSI_DCS_LONG_WRITE:
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dsi_xfer.sendDscCmd = true;
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dsi_xfer.dscCmd = msg->cmd;
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dsi_xfer.txDataType = kDSI_TxDataDcsShortWrOneParam;
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
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dsi_xfer.txDataType = kDSI_TxDataGenShortWrNoParam;
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
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dsi_xfer.txDataType = kDSI_TxDataGenShortWrOneParam;
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break;
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case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
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dsi_xfer.txDataType = kDSI_TxDataGenShortWrTwoParam;
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break;
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case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
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__fallthrough;
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case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
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__fallthrough;
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case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
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LOG_ERR("Generic Read not yet implemented or used");
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return -ENOTSUP;
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default:
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LOG_ERR("Unsupported message type (%d)", msg->type);
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return -ENOTSUP;
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}
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status = DSI_TransferBlocking(config->base, &dsi_xfer);
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if (status != kStatus_Success) {
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LOG_ERR("Transmission failed");
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return -EIO;
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}
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if (msg->rx_len != 0) {
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/* Return rx_len on a read */
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return msg->rx_len;
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}
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/* Return tx_len on a write */
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return msg->tx_len;
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}
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static struct mipi_dsi_driver_api dsi_mcux_api = {
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.attach = dsi_mcux_attach,
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.transfer = dsi_mcux_transfer,
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};
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static int mcux_mipi_dsi_init(const struct device *dev)
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{
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const struct mcux_mipi_dsi_config *config = dev->config;
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imxrt_pre_init_display_interface();
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if (!device_is_ready(config->bit_clk_dev) ||
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!device_is_ready(config->esc_clk_dev) ||
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!device_is_ready(config->pixel_clk_dev)) {
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return -ENODEV;
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}
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return 0;
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}
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#define MCUX_MIPI_DSI_DEVICE(id) \
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static const struct mcux_mipi_dsi_config mipi_dsi_config_##id = { \
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.base = (MIPI_DSI_HOST_Type *)DT_INST_REG_ADDR(id), \
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.dpi_config = { \
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.dpiColorCoding = DT_INST_ENUM_IDX(id, dpi_color_coding), \
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.pixelPacket = DT_INST_ENUM_IDX(id, dpi_pixel_packet), \
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.videoMode = DT_INST_ENUM_IDX(id, dpi_video_mode), \
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.bllpMode = DT_INST_ENUM_IDX(id, dpi_bllp_mode), \
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.pixelPayloadSize = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, width), \
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.panelHeight = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, height), \
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.polarityFlags = DT_INST_PROP_BY_PHANDLE_IDX( \
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id, nxp_lcdif, id, polarity) & 0x3, \
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.hfp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hfp), \
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.hbp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hbp), \
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.hsw = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, hsync), \
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.vfp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vfp), \
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.vbp = DT_INST_PROP_BY_PHANDLE(id, nxp_lcdif, vbp), \
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}, \
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.auto_insert_eotp = DT_INST_PROP(id, autoinsert_eotp), \
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.dphy_ref_freq = DT_INST_PROP_OR(id, dphy_ref_frequency, 0), \
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.bit_clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(id, dphy)), \
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.bit_clk_subsys = \
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(clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(id, dphy, name), \
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.esc_clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(id, esc)), \
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.esc_clk_subsys = \
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(clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(id, esc, name), \
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.pixel_clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(id, pixel)), \
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.pixel_clk_subsys = \
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(clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(id, pixel, name), \
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}; \
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DEVICE_DT_INST_DEFINE(id, \
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&mcux_mipi_dsi_init, \
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NULL, \
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NULL, \
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&mipi_dsi_config_##id, \
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POST_KERNEL, \
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CONFIG_MIPI_DSI_INIT_PRIORITY, \
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&dsi_mcux_api);
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DT_INST_FOREACH_STATUS_OKAY(MCUX_MIPI_DSI_DEVICE)

‎dts/bindings/mipi-dsi/nxp,mipi-dsi-2l.yaml

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#
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# Copyright 2023, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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description: NXP MCUX MIPI DSI 2L
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compatible: "nxp,mipi-dsi-2l"
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include: mipi-dsi-host.yaml
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properties:
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interrupts:
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required: true
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nxp,lcdif:
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type: phandle
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required: true
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description:
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Instance of the LCDIF peripheral.
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dpi-color-coding:
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type: string
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enum:
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- "16-bit-config-1"
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- "16-bit-config-2"
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- "16-bit-config-3"
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- "18-bit-config-1"
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- "18-bit-config-2"
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- "24-bit"
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description:
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MIPI DPI interface color coding. Sets the distribution of RGB bits within
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the 24-bit d bus, as specified by the DPI specification.
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dpi-pixel-packet:
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type: string
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enum:
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- "16-bit"
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- "18-bit"
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- "18-bit-loose"
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- "24-bit"
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description:
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MIPI DSI pixel packet type send through DPI interface.
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dpi-video-mode:
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type: string
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enum:
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- "non-burst-sync-pulse"
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- "non-burst-sync-event"
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- "burst"
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description:
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DPI video mode.
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dpi-bllp-mode:
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type: string
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enum:
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- "low-power"
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- "blank"
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- "null"
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description:
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Behavior in BLLP (Blanking or Low-Power Interval).
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autoinsert-eotp:
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type: boolean
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description:
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Automatically insert an EoTp short packet when switching from HS to LP mode.
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dphy-clk-div:
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type: int
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required: true
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description:
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MIPI D-PHY clock divider. Must be set to ensure clock frequency is at
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least (pixel clock * bits per output pixel) / number of mipi data lanes
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dphy-ref-frequency:
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type: int
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default: 0
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description:
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Maximum clock speed supported by the device, in Hz. Leave at default
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if no DPHY PLL is present

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