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ChiHuaLnashif
ChiHuaL
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drivers: spi: npcx: add SPI support to access the SPI flash
The FIU/UMA module in the NPCX chip provides an dedicated SPI interface to access the SPI flash. This commit adds the driver support for it. With this commit, the application can call the flash APIs (via spi_nor.c) to access the internal flash of NPCX EC chips. Signed-off-by: Jun Lin <[email protected]> Change-Id: I32bbf09f6e014b728ff8e4692e48151ae759e188
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‎drivers/spi/CMakeLists.txt‎

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@@ -25,5 +25,6 @@ zephyr_library_sources_ifdef(CONFIG_SPI_XLNX_AXI_QUADSPI spi_xlnx_axi_quadspi.c)
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zephyr_library_sources_ifdef(CONFIG_ESP32_SPIM spi_esp32_spim.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_TEST spi_test.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6 spi_psoc6.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_NPCX_FIU spi_npcx_fiu.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE spi_handlers.c)

‎drivers/spi/Kconfig‎

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@@ -84,4 +84,6 @@ source "drivers/spi/Kconfig.test"
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source "drivers/spi/Kconfig.psoc6"
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source "drivers/spi/Kconfig.npcx_fiu"
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endif # SPI

‎drivers/spi/Kconfig.npcx_fiu‎

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# NPCX SPI Driver configuration options
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# Copyright (c) 2021 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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config SPI_NPCX_FIU
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bool "Nuvoton NPCX embedded controller (EC) SPI driver for NOR flash"
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depends on SOC_FAMILY_NPCX
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help
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Enable the SPI driver for NPCX family of processors. This driver is
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for the dedicated SPI controller (FIU) to access the NOR flash.

‎drivers/spi/spi_npcx_fiu.c‎

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/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_spi_fiu
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#include <drivers/clock_control.h>
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#include <drivers/spi.h>
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#include <logging/log.h>
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#include <soc.h>
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LOG_MODULE_REGISTER(spi_npcx_fiu, LOG_LEVEL_ERR);
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#include "spi_context.h"
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/* Device config */
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struct npcx_spi_fiu_config {
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/* flash interface unit base address */
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uintptr_t base;
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/* clock configuration */
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struct npcx_clk_cfg clk_cfg;
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};
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/* Device data */
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struct npcx_spi_fiu_data {
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struct spi_context ctx;
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};
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/* Driver convenience defines */
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#define DRV_CONFIG(dev) ((const struct npcx_spi_fiu_config *)(dev)->config)
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#define DRV_DATA(dev) ((struct npcx_spi_fiu_data *)(dev)->data)
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#define HAL_INSTANCE(dev) (struct fiu_reg *)(DRV_CONFIG(dev)->base)
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static inline void spi_npcx_fiu_cs_level(const struct device *dev, int level)
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{
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struct fiu_reg *const inst = HAL_INSTANCE(dev);
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/* Set chip select to high/low level */
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if (level == 0)
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inst->UMA_ECTS &= ~BIT(NPCX_UMA_ECTS_SW_CS1);
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else
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inst->UMA_ECTS |= BIT(NPCX_UMA_ECTS_SW_CS1);
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}
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static inline void spi_npcx_fiu_exec_cmd(const struct device *dev, uint8_t code,
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uint8_t cts)
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{
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struct fiu_reg *const inst = HAL_INSTANCE(dev);
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#ifdef CONFIG_ASSERT
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struct npcx_spi_fiu_data *data = DRV_DATA(dev);
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struct spi_context *ctx = &data->ctx;
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/* Flash mutex must be held while executing UMA commands */
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__ASSERT((k_sem_count_get(&ctx->lock) == 0), "UMA is not locked");
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#endif
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/* set UMA_CODE */
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inst->UMA_CODE = code;
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/* execute UMA flash transaction */
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inst->UMA_CTS = cts;
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while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE))
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continue;
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}
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static int spi_npcx_fiu_transceive(const struct device *dev,
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const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct npcx_spi_fiu_data *data = DRV_DATA(dev);
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struct fiu_reg *const inst = HAL_INSTANCE(dev);
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struct spi_context *ctx = &data->ctx;
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size_t cur_xfer_len;
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int error = 0;
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spi_context_lock(ctx, false, NULL, spi_cfg);
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/*
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* Configure UMA lock/unlock only if tx buffer set and rx buffer set
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* are both empty.
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*/
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if (tx_bufs == NULL && rx_bufs == NULL) {
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if (spi_cfg->operation & SPI_LOCK_ON)
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inst->UMA_ECTS |= BIT(NPCX_UMA_ECTS_UMA_LOCK);
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else
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inst->UMA_ECTS &= ~BIT(NPCX_UMA_ECTS_UMA_LOCK);
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spi_context_unlock_unconditionally(ctx);
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return 0;
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}
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/* Assert chip assert */
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spi_npcx_fiu_cs_level(dev, 0);
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spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1);
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if (rx_bufs == NULL) {
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while (spi_context_tx_buf_on(ctx)) {
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spi_npcx_fiu_exec_cmd(dev, *ctx->tx_buf,
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UMA_CODE_CMD_WR_ONLY);
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spi_context_update_tx(ctx, 1, 1);
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}
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} else {
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cur_xfer_len = spi_context_longest_current_buf(ctx);
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for (size_t i = 0; i < cur_xfer_len; i++) {
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spi_npcx_fiu_exec_cmd(dev, *ctx->tx_buf,
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UMA_CODE_CMD_WR_ONLY);
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spi_context_update_tx(ctx, 1, 1);
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spi_context_update_rx(ctx, 1, 1);
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}
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while (spi_context_rx_buf_on(ctx)) {
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inst->UMA_CTS = UMA_CODE_RD_BYTE(1);
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while (IS_BIT_SET(inst->UMA_CTS,
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NPCX_UMA_CTS_EXEC_DONE))
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continue;
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/* Get read transaction results */
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*ctx->rx_buf = inst->UMA_DB0;
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spi_context_update_tx(ctx, 1, 1);
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spi_context_update_rx(ctx, 1, 1);
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}
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}
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spi_npcx_fiu_cs_level(dev, 1);
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spi_context_release(ctx, error);
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return error;
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}
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int spi_npcx_fiu_release(const struct device *dev,
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const struct spi_config *config)
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{
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struct npcx_spi_fiu_data *data = DRV_DATA(dev);
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struct spi_context *ctx = &data->ctx;
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if (!spi_context_configured(ctx, config)) {
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return -EINVAL;
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}
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spi_context_unlock_unconditionally(ctx);
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return 0;
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}
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static int spi_npcx_fiu_init(const struct device *dev)
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{
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const struct npcx_spi_fiu_config *const config = DRV_CONFIG(dev);
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const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
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int ret;
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if (!device_is_ready(clk_dev)) {
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LOG_ERR("%s device not ready", clk_dev->name);
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return -ENODEV;
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}
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/* Turn on device clock first and get source clock freq. */
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ret = clock_control_on(clk_dev,
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(clock_control_subsys_t *)&config->clk_cfg);
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if (ret < 0) {
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LOG_ERR("Turn on FIU clock fail %d", ret);
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return ret;
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}
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/* Make sure the context is unlocked */
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spi_context_unlock_unconditionally(&DRV_DATA(dev)->ctx);
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return 0;
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}
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static struct spi_driver_api spi_npcx_fiu_api = {
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.transceive = spi_npcx_fiu_transceive,
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.release = spi_npcx_fiu_release,
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};
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static const struct npcx_spi_fiu_config npcx_spi_fiu_config = {
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.base = DT_INST_REG_ADDR(0),
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.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
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};
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static struct npcx_spi_fiu_data npcx_spi_fiu_data = {
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SPI_CONTEXT_INIT_LOCK(npcx_spi_fiu_data, ctx),
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};
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DEVICE_DT_INST_DEFINE(0, &spi_npcx_fiu_init, NULL, &npcx_spi_fiu_data,
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&npcx_spi_fiu_config, POST_KERNEL,
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CONFIG_SPI_INIT_PRIORITY, &spi_npcx_fiu_api);

‎dts/arm/nuvoton/npcx.dtsi‎

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status = "disabled";
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};
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};
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/* Dedicated SPI interface to access SPI flashes */
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spi_fiu0: spi@40020000 {
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compatible = "nuvoton,npcx-spi-fiu";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40020000 0x2000>;
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clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL1 2>;
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label = "SPI_FIU";
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};
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};
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soc-if {

‎dts/arm/nuvoton/npcx7m6fb.dtsi‎

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device-id = <0x21>;
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};
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};
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&spi_fiu0 {
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int_flash: w25q80@0 {
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compatible ="jedec,spi-nor";
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/* 8388608 bits = 1 Mbytes */
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size = <0x800000>;
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label = "W25Q80";
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reg = <0>;
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spi-max-frequency = <50000000>;
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status = "okay";
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jedec-id = [ef 40 14];
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};
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};

‎dts/arm/nuvoton/npcx7m6fc.dtsi‎

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device-id = <0x29>;
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};
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};
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&spi_fiu0 {
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int_flash: w25q40@0 {
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compatible ="jedec,spi-nor";
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/* 4194304 bits = 512K Bytes */
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size = <0x400000>;
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label = "W25Q40";
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reg = <0>;
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spi-max-frequency = <50000000>;
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status = "okay";
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jedec-id = [ef 40 13];
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};
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};

‎dts/arm/nuvoton/npcx7m7fc.dtsi‎

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device-id = <0x20>;
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};
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};
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&spi_fiu0 {
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int_flash: w25q40@0 {
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compatible ="jedec,spi-nor";
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/* 4194304 bits = 512K Bytes */
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size = <0x400000>;
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label = "W25Q40";
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reg = <0>;
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spi-max-frequency = <50000000>;
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status = "okay";
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jedec-id = [ef 40 13];
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};
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};

‎dts/arm/nuvoton/npcx9m3f.dtsi‎

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device-id = <0x25>;
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};
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};
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&spi_fiu0 {
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int_flash: w25q40@0 {
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compatible ="jedec,spi-nor";
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/* 4194304 bits = 512K Bytes */
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size = <0x400000>;
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label = "W25Q40";
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reg = <0>;
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spi-max-frequency = <50000000>;
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status = "okay";
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jedec-id = [ef 40 13];
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};
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};

‎dts/arm/nuvoton/npcx9m6f.dtsi‎

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device-id = <0x21>;
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};
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};
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&spi_fiu0 {
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int_flash: w25q40@0 {
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compatible ="jedec,spi-nor";
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/* 4194304 bits = 512K Bytes */
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size = <0x400000>;
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label = "W25Q40";
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reg = <0>;
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spi-max-frequency = <50000000>;
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status = "okay";
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jedec-id = [ef 40 13];
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};
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};

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