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Tomasz Bursztykanashif
Tomasz Bursztyka
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nashif
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drivers/pcie: Add Virtual Channel configuration support
Basic support of VC capability, where a driver can enable VC and map its traffic classes. Signed-off-by: Tomasz Bursztyka <[email protected]>
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3 files changed

+181
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lines changed

‎drivers/pcie/host/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
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@@ -1,6 +1,6 @@
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zephyr_library()
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3-
zephyr_library_sources(pcie.c)
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zephyr_library_sources(pcie.c vc.c)
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zephyr_library_sources_ifdef(CONFIG_PCIE_CONTROLLER controller.c)
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zephyr_library_sources_ifdef(CONFIG_PCIE_ECAM pcie_ecam.c)
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zephyr_library_sources_ifdef(CONFIG_PCIE_MSI msi.c)

‎drivers/pcie/host/vc.c

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/*
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* Copyright (c) 2023 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/pcie/pcie.h>
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#include <zephyr/drivers/pcie/cap.h>
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#include "vc.h"
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uint32_t pcie_vc_cap_lookup(pcie_bdf_t bdf, struct pcie_vc_regs *regs)
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{
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uint32_t base;
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base = pcie_get_ext_cap(bdf, PCIE_EXT_CAP_ID_VC);
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if (base == 0) {
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base = pcie_get_ext_cap(bdf, PCIE_EXT_CAP_ID_MFVC_VC);
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if (base == 0) {
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return 0;
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}
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}
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regs->cap_reg_1.raw = pcie_conf_read(bdf, base +
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PCIE_VC_CAP_REG_1_OFFSET);
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regs->cap_reg_2.raw = pcie_conf_read(bdf, base +
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PCIE_VC_CAP_REG_2_OFFSET);
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regs->ctrl_reg.raw = pcie_conf_read(bdf, base +
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PCIE_VC_CTRL_STATUS_REG_OFFSET);
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return base;
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}
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void pcie_vc_load_resources_regs(pcie_bdf_t bdf,
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uint32_t base,
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struct pcie_vc_resource_regs *regs,
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int nb_regs)
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{
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int idx;
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for (idx = 0; idx < nb_regs; idx++) {
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regs->cap_reg.raw =
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pcie_conf_read(bdf, base +
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PCIE_VC_RES_CAP_REG_OFFSET(idx));
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regs->ctrl_reg.raw =
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pcie_conf_read(bdf, base +
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PCIE_VC_RES_CTRL_REG_OFFSET(idx));
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regs->status_reg.raw =
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pcie_conf_read(bdf, base +
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PCIE_VC_RES_STATUS_REG_OFFSET(idx));
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regs++;
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}
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}

‎drivers/pcie/host/vc.h

Lines changed: 123 additions & 0 deletions
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/*
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* Copyright (c) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_PCIE_HOST_VC_H_
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#define ZEPHYR_DRIVERS_PCIE_HOST_VC_H_
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#define PCIE_VC_MAX_COUNT 8
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#define PCIE_VC_CAP_REG_1_OFFSET 0x04U
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#define PCIE_VC_CAP_REG_2_OFFSET 0x08U
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#define PCIE_VC_CTRL_STATUS_REG_OFFSET 0x0CU
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/** Virtual Channel capability and control Registers */
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struct pcie_vc_regs {
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union {
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struct {
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/** Virtual Channel Count */
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uint32_t vc_count : 3;
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uint32_t _reserved1 : 1;
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/** Low Priority Virtual Channel Count */
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uint32_t lpvc_count : 3;
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uint32_t _reserved2 : 1;
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/** Reference Clock */
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uint32_t reference_clock : 2;
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/** Port Arbitration Table Entry Size */
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uint32_t pat_entry_size : 3;
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uint32_t _reserved3 : 19;
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};
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uint32_t raw;
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} cap_reg_1;
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union {
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struct {
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/** Virtual Channel Arbitration Capability */
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uint32_t vca_cap : 8;
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uint32_t _reserved1 : 16;
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/** Virtual Channel Arbitration Table Offset */
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uint32_t vca_table_offset : 8;
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};
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uint32_t raw;
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} cap_reg_2;
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union {
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struct {
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/** Load Virtual Channel Arbitration Table */
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uint32_t load_vca_table : 1;
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/** Virtual Channel Arbitration Select */
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uint32_t vca_select : 3;
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uint32_t _reserved1 : 12;
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/** Virtual Channel Arbitration Table Status */
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uint32_t vca_table_status : 1;
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uint32_t _reserved2 : 15;
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};
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uint32_t raw;
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} ctrl_reg;
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};
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#define PCIE_VC_RES_CAP_REG_OFFSET(_vc) (0x10U + _vc * 0X0CU)
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#define PCIE_VC_RES_CTRL_REG_OFFSET(_vc) (0x14U + _vc * 0X0CU)
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#define PCIE_VC_RES_STATUS_REG_OFFSET(_vc) (0x18U + _vc * 0X0CU)
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/** Virtual Channel Resource Registers */
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struct pcie_vc_resource_regs {
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union {
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struct {
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/** Port Arbitration Capability */
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uint32_t pa_cap : 8;
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uint32_t _reserved1 : 6;
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uint32_t undefined : 1;
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/** Reject Snoop Transactions */
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uint32_t rst : 1;
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/** Maximum Time Slots */
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uint32_t max_time_slots : 7;
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uint32_t _reserved2 : 1;
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/** Port Arbitration Table Offset */
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uint32_t pa_table_offset : 8;
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};
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uint32_t raw;
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} cap_reg;
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union {
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struct {
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/** Traffic Class to Virtual Channel Map */
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uint32_t tc_vc_map : 8;
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uint32_t _reserved1 : 8;
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/** Load Port Arbitration Table */
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uint32_t load_pa_table : 1;
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/** Port Arbitration Select */
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uint32_t pa_select : 3;
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uint32_t _reserved2 : 4;
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/** Virtual Channel ID */
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uint32_t vc_id : 3;
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uint32_t _reserved3 : 4;
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/** Virtual Channel Enable */
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uint32_t vc_enable : 1;
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};
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uint32_t raw;
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} ctrl_reg;
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union {
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struct {
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uint32_t _reserved1 : 16;
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/** Port Arbitration Table Status */
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uint32_t pa_table_status : 1;
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/** Virtual Channel Negociation Pending */
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uint32_t vc_negocation_pending : 1;
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uint32_t _reserved2 : 14;
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};
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uint32_t raw;
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} status_reg;
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};
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uint32_t pcie_vc_cap_lookup(pcie_bdf_t bdf, struct pcie_vc_regs *regs);
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void pcie_vc_load_resources_regs(pcie_bdf_t bdf,
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uint32_t base,
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struct pcie_vc_resource_regs *regs,
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int nb_regs);
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#endif /* ZEPHYR_DRIVERS_PCIE_HOST_VC_H_ */

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