drivers: pinctrl: Add pinctrl driver for SOPHGO CVI series

This commit introduces a pin-controller driver for the CVI series SoCs by
SOPHGO.

Predefined pinmux values are also added. Please refer to the official
datasheet for the naming conventions of pins and signals.

Signed-off-by: Chen Xingyu <[email protected]>

Author: xingrz

drivers/pinctrl/CMakeLists.txt

@@ -54,5 +54,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_SY1XX pinctrl_sy1xx.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_REALTEK_RTS5912 pinctrl_realtek_rts5912.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x_afio.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_00X_AFIO pinctrl_wch_00x_afio.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_SOPHGO_CVI pinctrl_sophgo_cvi.c)
 
 add_subdirectory(renesas)

drivers/pinctrl/Kconfig

@@ -81,6 +81,7 @@ source "drivers/pinctrl/Kconfig.sy1xx"
 source "drivers/pinctrl/Kconfig.realtek_rts5912"
 source "drivers/pinctrl/Kconfig.wch_20x_30x_afio"
 source "drivers/pinctrl/Kconfig.wch_00x_afio"
+source "drivers/pinctrl/Kconfig.sophgo"
 
 rsource "renesas/Kconfig"
 

drivers/pinctrl/Kconfig.sophgo

@@ -0,0 +1,9 @@
+# Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_SOPHGO_CVI
+	bool "SOPHGO CVI series pin controller driver"
+	default y
+	depends on DT_HAS_SOPHGO_CVI_PINCTRL_ENABLED
+	help
+	  Enables support for the SOPHGO CVI series pin controller.

drivers/pinctrl/pinctrl_sophgo_cvi.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT sophgo_cvi_pinctrl
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/pinctrl.h>
+
+#define PINCTRL_BASE DT_INST_REG_ADDR(0)
+
+#define PINCTRL_FMUX(n) (0x00 + (n) * 4)
+
+#define FMUX_MASK BIT_MASK(3)
+
+static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
+{
+	uint32_t regval;
+
+	regval = sys_read32(PINCTRL_BASE + PINCTRL_FMUX(pin->fmux_idx));
+	regval &= ~FMUX_MASK;
+	regval |= pin->fmux_sel;
+	sys_write32(regval, PINCTRL_BASE + PINCTRL_FMUX(pin->fmux_idx));
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+
+	for (uint8_t i = 0; i < pin_cnt; i++) {
+		pinctrl_configure_pin(&pins[i]);
+	}
+
+	return 0;
+}

dts/bindings/pinctrl/sophgo,cvi-pinctrl.yaml

@@ -0,0 +1,17 @@
+# Copyright (c) 2023-2024 Chen Xingyu <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+description: SOPHGO CVI series pin controller driver
+
+compatible: "sophgo,cvi-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: CVI pinmux group
+
+  child-binding:
+    properties:
+      pinmux:
+        required: true
+        type: array

dts/riscv/sophgo/cv180x.dtsi

@@ -7,11 +7,17 @@
 #include <freq.h>
 
 #include <sophgo/cv18xx-c906-common.dtsi>
+#include <zephyr/dt-bindings/pinctrl/sophgo-cv180x-pinctrl.h>
 
 / {
 	soc {
 		compatible = "sophgo,cv180x", "simple-bus";
 
+		pinctrl: pin-controller@3001000 {
+			compatible = "sophgo,cvi-pinctrl";
+			reg = <0x3001000 DT_SIZE_K(4)>;
+		};
+
 		gpioa: gpio@3020000 {
 			compatible = "snps,designware-gpio";
 			reg = <0x3020000 DT_SIZE_K(4)>;

dts/riscv/sophgo/cv181x.dtsi

@@ -7,11 +7,17 @@
 #include <freq.h>
 
 #include <sophgo/cv18xx-c906-common.dtsi>
+#include <zephyr/dt-bindings/pinctrl/sophgo-cv181x-pinctrl.h>
 
 / {
 	soc {
 		compatible = "sophgo,cv181x", "simple-bus";
 
+		pinctrl: pin-controller@3001000 {
+			compatible = "sophgo,cvi-pinctrl";
+			reg = <0x3001000 DT_SIZE_K(4)>;
+		};
+
 		gpioa: gpio@3020000 {
 			compatible = "snps,designware-gpio";
 			reg = <0x3020000 DT_SIZE_K(4)>;