boards: arm: fvp: Add Cortex-A320 board variant support

Add Cortex-A320 support to the unified FVP board structure with ARMv9.2-A
specific configuration parameters.

New board target:
- fvp_base_revc_2xaem/a320

Signed-off-by: Nicolas Pitre <[email protected]>

Author: Nicolas Pitre

arch/arm64/core/Kconfig

@@ -89,6 +89,16 @@ config CPU_CORTEX_A510
 	  power-efficient processing optimized for embedded applications with
 	  ARMv9-A features.
 
+config CPU_CORTEX_A320
+	bool
+	select CPU_CORTEX_A
+	select ARMV9_A
+	help
+	  This option signifies the use of a Cortex-A320 CPU, which implements
+	  the ARMv9.2-A architecture. It provides advanced features including
+	  enhanced SVE2, improved security extensions, and specialized performance
+	  optimizations.
+
 config CPU_CORTEX_R82
 	bool
 	select CPU_AARCH64_CORTEX_R

boards/arm/fvp_base_revc_2xaem/Kconfig.fvp_base_revc_2xaem

@@ -10,3 +10,4 @@ config BOARD_FVP_BASE_REVC_2XAEM
 	select SOC_FVP_V9A if BOARD_QUALIFIERS = "v9a"
 	select SOC_FVP_V9A if BOARD_QUALIFIERS = "v9a/smp"
 	select SOC_FVP_V9A if BOARD_QUALIFIERS = "v9a/smp/ns"
+	select SOC_FVP_A320 if BOARD_QUALIFIERS = "a320"

boards/arm/fvp_base_revc_2xaem/board.cmake

@@ -50,6 +50,88 @@ if(CONFIG_ARMV9_A)
   set(ARMFVP_MIN_VERSION 11.29.27)
 endif()
 
+# Add Cortex-A320 specific configuration flags
+if(CONFIG_BOARD_FVP_BASE_REVC_2XAEM_A320)
+  set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
+    # Cortex-A320 specific CPU identification
+    -C cluster0.MIDR=0x410FD8F0
+    -C cluster0.AMIIDR=0xD8F0043B
+    -C cluster0.AMPIDR=0x4000BBD8F
+    -C cluster0.ERRIIDR=0xD8F0043B
+    -C cluster0.ERRPIDR=0x4000BBD8F
+    -C cluster0.PMUPIDR=0x4000BBD80
+    -C cluster0.CTIPIDR=0x4003BBD8F
+    -C cluster0.DBGPIDR=0x4003BBD8F
+
+    # ARMv9.2-A support level
+    -C cluster0.has_arm_v9-2=1
+
+    # Advanced SIMD and crypto support
+    -C cluster0.advsimd_bf16_support_level=1
+    -C cluster0.advsimd_i8mm_support_level=1
+    -C cluster0.cpu0.crypto_sha3=1
+    -C cluster0.cpu0.crypto_sha512=1
+    -C cluster0.cpu0.crypto_sm3=1
+    -C cluster0.cpu0.crypto_sm4=1
+    -C cluster0.cpu0.enable_crc32=1
+
+    # Memory tagging support
+    -C cluster0.memory_tagging_support_level=3
+
+    # Enhanced security features
+    -C cluster0.has_qarma3_pac=1
+    -C cluster0.has_const_pac=2
+
+    # SVE configuration for Cortex-A320
+    -C cluster0.sve.veclen=2
+
+    # Performance monitoring
+    -C cluster0.pmu-num_counters=6
+    -C cluster0.configure_pmu_events_with_json='{"pmu_events":["SVE_INST_RETIRED","BR_INDNR_TAKEN_RETIRED","BR_IND_RETIRED","EXC_IRQ","EXC_FIQ","EXC_RETURN","EXC_TAKEN","L1D_CACHE_RD","L2D_CACHE_RD","BUS_ACCESS_RD","BUS_ACCESS_WR","MEM_ACCESS_RD","MEM_ACCESS_WR","BR_PRED_RETIRED","BR_IMMED_MIS_PRED_RETIRED","BR_IND_MIS_PRED_RETIRED","BR_RETURN_PRED_RETIRED","BR_RETURN_MIS_PRED_RETIRED","BR_INDNR_PRED_RETIRED","BR_INDNR_MIS_PRED_RETIRED","BR_IMMED_PRED_RETIRED"]}'
+
+    # Cache configuration
+    -C cluster0.dcache-ways=4
+    -C cluster0.icache-ways=4
+    -C cluster0.l2cache-ways=8
+    -C cluster0.icache-log2linelen=6
+    -C cluster0.l2cache-read_bus_width_in_bytes=16
+    -C cluster0.l2cache-write_bus_width_in_bytes=32
+
+    # Debug and trace configuration
+    -C cluster0.has_ets=1
+    -C cluster0.has_trbe=1
+    -C cluster0.has_self_hosted_trace_extension=2
+
+    # Advanced architectural features
+    -C cluster0.has_ccidx=1
+    -C cluster0.has_16k_granule=1
+    -C cluster0.ecv_support_level=2
+    -C cluster0.has_cvadp_support=1
+    -C cluster0.has_lrcpc=1
+    -C cluster0.has_dot_product=2
+    -C cluster0.has_wfet_and_wfit=2
+    -C cluster0.has_xs=2
+    -C cluster0.has_v8_5_debug_over_power_down=2
+    -C cluster0.has_no_os_double_lock=1
+    -C cluster0.has_v8_7_fp_enhancements=2
+    -C cluster0.has_amu=1
+    -C cluster0.has_mpmm=1
+    -C cluster0.has_mpam=2
+    -C cluster0.has_ras=2
+
+    # Memory system configuration
+    -C cluster0.stage12_tlb_size=1024
+    -C cluster0.restriction_on_speculative_execution=2
+    -C cluster0.restriction_on_speculative_execution_aarch32=2
+
+    # Error handling
+    -C cluster0.number_of_error_records=3
+    -C cluster0.ERXMISC0_mask=0xC003FFC3
+    )
+  # Set minimum FVP version for Cortex-A320 features
+  set(ARMFVP_MIN_VERSION 11.29.27)
+endif()
+
 if(CONFIG_BUILD_WITH_TFA)
   set(TFA_PLAT "fvp")
 

boards/arm/fvp_base_revc_2xaem/board.yml

@@ -13,3 +13,4 @@ board:
     - name: smp
       variants:
       - name: ns
+  - name: a320

boards/arm/fvp_base_revc_2xaem/doc/index.rst

@@ -41,14 +41,27 @@ The kernel currently does not support other hardware features on this platform.
 Board Variants
 ==============
 
-The following board targets are available:
+The following targets are available:
 
 * ``fvp_base_revc_2xaem/v8a`` - ARMv8-A (64-bit) with Cortex-A53 cores
 * ``fvp_base_revc_2xaem/v8a/smp`` - ARMv8-A SMP (4 cores)
 * ``fvp_base_revc_2xaem/v8a/smp/ns`` - ARMv8-A SMP Non-Secure
 * ``fvp_base_revc_2xaem/v9a`` - ARMv9-A (64-bit) with Cortex-A510 cores
 * ``fvp_base_revc_2xaem/v9a/smp`` - ARMv9-A SMP (4 cores)
 * ``fvp_base_revc_2xaem/v9a/smp/ns`` - ARMv9-A SMP Non-Secure
+* ``fvp_base_revc_2xaem/a320`` - ARMv9.2-A with Cortex-A320 configuration
+
+**Cortex-A320 Variant:**
+
+The ``fvp_base_revc_2xaem/a320`` variant provides Cortex-A320 specific FVP
+configuration with:
+
+* ARMv9.2-A architecture compliance
+* Enhanced cryptographic extensions (SHA3, SHA512, SM3, SM4)
+* Advanced memory tagging (MTE Level 3)
+* QARMA3 Pointer Authentication
+* Optimized cache configuration for Cortex-A320
+* Performance monitoring unit with SVE-specific events
 
 Devices
 ========
@@ -103,6 +116,14 @@ For ARMv9-A variants:
    :board: fvp_base_revc_2xaem/v9a
    :goals: build
 
+For Cortex-A320 specific configuration:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :host-os: unix
+   :board: fvp_base_revc_2xaem/a320
+   :goals: build
+
 For SMP variants:
 
 .. zephyr-app-commands::

boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_a320.dts

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 BayLibre SAS
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm64/armv9-a.dtsi>
+#include "fvp_base_revc_2xaem.dtsi"
+
+/ {
+	model = "FVP Base RevC 2xAEMv9A (Cortex-A320)";
+};
+
+&cpu0 {
+	compatible = "arm,cortex-a320";
+};
+
+&cpu1 {
+	compatible = "arm,cortex-a320";
+};
+
+&cpu2 {
+	compatible = "arm,cortex-a320";
+};
+
+&cpu3 {
+	compatible = "arm,cortex-a320";
+};

boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_a320.yaml

@@ -0,0 +1,16 @@
+# Copyright (c) 2025 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: fvp_base_revc_2xaem/a320
+name: FVP Emulation FVP_Base_RevC-2xAEMv9A (Cortex-A320)
+arch: arm64
+type: sim
+simulation:
+  - name: armfvp
+    exec: FVP_Base_RevC-2xAEMvA
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 2048
+flash: 64
+vendor: arm

boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_a320_defconfig

@@ -0,0 +1,20 @@
+# Copyright (c) 2025 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+CONFIG_THREAD_STACK_INFO=y
+
+# Enable Timer and Sys clock
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_ARM_ARCH_TIMER=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable serial port
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

cmake/gcc-m-cpu.cmake

@@ -117,6 +117,12 @@ elseif("${ARCH}" STREQUAL "arm64")
     set(GCC_M_CPU cortex-a78)
   elseif(CONFIG_CPU_CORTEX_A510)
     set(GCC_M_CPU cortex-a510)
+  elseif(CONFIG_CPU_CORTEX_A320)
+    # Cortex-A320 was announced in February 2025 and is not yet supported in any GCC version
+    # Use cortex-a710 as fallback since both are high-performance ARMv9-A cores with similar features
+    # TODO: Update to use cortex-a320 when GCC support is added (likely in GCC 15 or 16)
+    set(GCC_M_CPU cortex-a710)
+    message(STATUS "Using cortex-a710 as fallback for cortex-a320 (not yet supported in GCC)")
   elseif(CONFIG_CPU_CORTEX_R82)
     set(GCC_M_CPU cortex-r82)
   endif()

doc/releases/release-notes-4.3.rst

@@ -123,6 +123,7 @@ New APIs and options
       * fvp_base_revc_2xaem/v9a (basic ARMv9-A single core)
       * fvp_base_revc_2xaem/v9a/smp (ARMv9-A SMP 4 cores)
       * fvp_base_revc_2xaem/v9a/smp/ns (ARMv9-A SMP non-secure with TFA)
+      * fvp_base_revc_2xaem/a320 (Cortex-A320 specific)
 
 * Bluetooth