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soc: renesas: Add initial support for RA6M4 SoC
- Initial support for RA6M4 SoC Signed-off-by: Duy Phuong Hoang. Nguyen <[email protected]>
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‎dts/arm/renesas/ra/ra6/r7fa6m4af3cfb.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra6/r7fa6m4ax.dtsi>
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/ {
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soc {
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flash-controller@407e0000 {
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reg = <0x407e0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_M(1)>;
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};
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};
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};
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};

‎dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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/ {
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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sci1: sci1@40118100 {
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compatible = "renesas,ra-sci";
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interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118100 0x100>;
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clocks = <&pclka MSTPB 30>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <1>;
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status = "disabled";
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};
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};
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sci2: sci2@40118200 {
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compatible = "renesas,ra-sci";
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interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118200 0x100>;
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clocks = <&pclka MSTPB 29>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <2>;
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status = "disabled";
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};
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};
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sci3: sci3@40118300 {
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compatible = "renesas,ra-sci";
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interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118300 0x100>;
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clocks = <&pclka MSTPB 28>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <3>;
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status = "disabled";
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};
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};
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sci4: sci4@40118400 {
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compatible = "renesas,ra-sci";
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interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118400 0x100>;
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clocks = <&pclka MSTPB 27>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <4>;
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status = "disabled";
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};
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};
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sci5: sci5@40118500 {
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compatible = "renesas,ra-sci";
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interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118500 0x100>;
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clocks = <&pclka MSTPB 26>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <5>;
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status = "disabled";
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};
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};
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sci6: sci6@40118600 {
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compatible = "renesas,ra-sci";
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interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118600 0x100>;
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clocks = <&pclka MSTPB 25>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <6>;
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status = "disabled";
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};
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};
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sci7: sci7@40118700 {
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compatible = "renesas,ra-sci";
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interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118700 0x100>;
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clocks = <&pclka MSTPB 24>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <7>;
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status = "disabled";
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};
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};
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sci8: sci8@40118800 {
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compatible = "renesas,ra-sci";
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interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118800 0x100>;
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clocks = <&pclka MSTPB 23>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <8>;
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status = "disabled";
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};
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};
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};
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clocks: clocks {
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xtal: clock-xtal {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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source = <RA_PLL_SOURCE_MAIN_OSC>;
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div = <RA_PLL_DIV_3>;
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mul = <25 0>;
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status = "disabled";
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};
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pll2: pll2 {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL2 */
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source = <RA_PLL_SOURCE_DISABLE>;
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div = <RA_PLL_DIV_2>;
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mul = <20 0>;
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status = "disabled";
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};
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pclkblock: pclkblock {
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compatible = "renesas,ra-cgc-pclk-block";
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#clock-cells = <0>;
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sysclock-src = <RA_CLOCK_SOURCE_PLL>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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bclk: bclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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bclkout: bclkout {
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compatible = "renesas,ra-cgc-busclk";
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clk_out_div = <2>;
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sdclk = <0>;
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#clock-cells = <0>;
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};
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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uclk: uclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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octaspiclk: octaspiclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};

‎soc/renesas/ra/ra6m4/CMakeLists.txt‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/ra/ra6m4/Kconfig‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA6M4
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select ARM
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select HAS_RENESAS_RA_FSP
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select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select FPU
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select HAS_SWO
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select XIP

‎soc/renesas/ra/ra6m4/Kconfig.defconfig‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA6M4
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config NUM_IRQS
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default 96
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config PINCTRL
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default y
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endif # SOC_SERIES_RA6M4

‎soc/renesas/ra/ra6m4/Kconfig.soc‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA6M4
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bool
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select SOC_FAMILY_RENESAS_RA
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help
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Renesas RA6M4 series
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config SOC_R7FA6M4AF3CFB
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bool
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select SOC_SERIES_RA6M4
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help
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R7FA6M4AF3CFB
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config SOC_SERIES
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default "ra6m4" if SOC_SERIES_RA6M4
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config SOC
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default "r7fa6m4af3cfb" if SOC_R7FA6M4AF3CFB

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