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soc: renesas: Add initial support for RA6M2 SoC
- Initial support for RA6M2 SoC Signed-off-by: Tri Nguyen <[email protected]> Signed-off-by: Danh Doan <[email protected]> Signed-off-by: Duy Phuong Hoang. Nguyen <[email protected]>
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‎dts/arm/renesas/ra/ra6/r7fa6m2af3cfb.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra6/r7fa6m2ax.dtsi>
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/ {
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soc {
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flash-controller@407e0000 {
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compatible = "renesas,ra6-flash-controller";
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reg = <0x407e0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <4 1>, <5 1>;
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interrupt-names = "frdyi", "fiferr";
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_M(1)>;
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write-block-size = <128>;
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erase-block-size = <8192>;
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};
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};
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};
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};

‎dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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/ {
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soc {
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sram0: memory@1ffe0000 {
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compatible = "mmio-sram";
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reg = <0x1ffe0000 DT_SIZE_K(384)>;
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};
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sci5: sci5@400700a0 {
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compatible = "renesas,ra-sci";
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interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x400700a0 0x20>;
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clocks = <&pclka MSTPB 26>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <5>;
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status = "disabled";
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};
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};
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sci6: sci6@400700c0 {
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compatible = "renesas,ra-sci";
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interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x400700c0 0x20>;
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clocks = <&pclka MSTPB 25>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <6>;
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status = "disabled";
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};
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};
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sci7: sci7@400700e0 {
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compatible = "renesas,ra-sci";
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interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x400700e0 0x20>;
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clocks = <&pclka MSTPB 24>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <7>;
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status = "disabled";
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};
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};
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};
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clocks: clocks {
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xtal: clock-xtal {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(12)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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source = <RA_PLL_SOURCE_MAIN_OSC>;
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div = <RA_PLL_DIV_1>;
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mul = <20 0>;
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status = "disabled";
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};
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pclkblock: pclkblock {
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compatible = "renesas,ra-cgc-pclk-block";
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#clock-cells = <0>;
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sysclock-src = <RA_CLOCK_SOURCE_PLL>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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bclk: bclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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bclkout: bclkout {
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compatible = "renesas,ra-cgc-busclk";
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clk_out_div = <2>;
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sdclk = <1>;
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#clock-cells = <0>;
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};
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#clock-cells = <2>;
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status = "okay";
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};
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uclk: uclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_USB_CLOCK_DIV_5>;
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};

‎soc/renesas/ra/ra6m2/CMakeLists.txt‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_linker_sources(ROM_START opt_set_mem.ld)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/ra/ra6m2/Kconfig‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA6M2
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select ARM
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select CPU_CORTEX_M4
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select CPU_HAS_ARM_MPU
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select HAS_RENESAS_RA_FSP
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select FPU
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select HAS_SWO
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select XIP

‎soc/renesas/ra/ra6m2/Kconfig.defconfig‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA6M2
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config NUM_IRQS
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default 96
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config PINCTRL
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default y
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endif # SOC_SERIES_RA6M2

‎soc/renesas/ra/ra6m2/Kconfig.soc‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA6M2
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bool
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select SOC_FAMILY_RENESAS_RA
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help
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Renesas RA6M2 series
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config SOC_R7FA6M2AF3CFB
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bool
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select SOC_SERIES_RA6M2
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help
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R7FA6M2AF3CFB
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config SOC_SERIES
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default "ra6m2" if SOC_SERIES_RA6M2
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config SOC
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default "r7fa6m2af3cfb" if SOC_R7FA6M2AF3CFB

‎soc/renesas/ra/ra6m2/opt_set_mem.ld‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ROM Registers start at address 0x00000400 */
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. = 0x400;
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KEEP(*(.rom_registers*))
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/* Reserving 0x100 bytes of space for ROM registers. */
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. = 0x500;

‎soc/renesas/ra/ra6m2/sections.ld‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.code_in_ram :
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{
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. = ALIGN(4);
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__Code_In_RAM_Start = .;
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KEEP(*(.code_in_ram*))
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__Code_In_RAM_End = .;
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} > RAMABLE_REGION
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SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
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{
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/* If DTC is used, put the DTC vector table at the start of SRAM.
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This avoids memory holes due to 1K alignment required by it. */
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*(.fsp_dtc_vector_table)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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SECTION_PROLOGUE(.id_code,,)
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{
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KEEP(*(.id_code*))
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} GROUP_LINK_IN(ID_CODE)

‎soc/renesas/ra/ra6m2/soc.c‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Renesas RA6M2 family processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <cmsis_core.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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#include "bsp_cfg.h"
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#include <bsp_api.h>
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uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
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volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int renesas_ra6m2_init(void)
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{
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uint32_t key;
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key = irq_lock();
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SystemCoreClock = BSP_MOCO_HZ;
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g_protect_pfswe_counter = 0;
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bsp_clock_init();
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irq_unlock(key);
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return 0;
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}
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SYS_INIT(renesas_ra6m2_init, PRE_KERNEL_1, 0);

‎soc/renesas/ra/ra6m2/soc.h‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the Renesas RA6M2 family MCU
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_
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#include <bsp_api.h>
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#endif /* ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_ */

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