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drivers: usb: dwc2: Added host register set
Added register bitmask description with low-level abstraction Signed-off-by: Roman Leonov <[email protected]>
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‎drivers/usb/common/usb_dwc2_hw.h‎

Lines changed: 194 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,18 @@ struct usb_dwc2_out_ep {
4040
volatile uint32_t doepdmab;
4141
};
4242

43+
/* HOST channer register block */
44+
struct usb_dwc2_host_chan {
45+
volatile uint32_t hcchar;
46+
volatile uint32_t hcsplt;
47+
volatile uint32_t hcint;
48+
volatile uint32_t hcintmsk;
49+
volatile uint32_t hctsiz;
50+
volatile uint32_t hcdma;
51+
volatile uint32_t reserved_0x18[1];
52+
volatile uint32_t hcdmab;
53+
};
54+
4355
/* DWC2 register map
4456
* TODO: This should probably be split into global, host, and device register
4557
* blocks
@@ -80,8 +92,20 @@ struct usb_dwc2_reg {
8092
volatile uint32_t dieptxf[15];
8193
};
8294
volatile uint32_t reserved2[176];
83-
/* Host mode register 0x0400 .. 0x0670 */
84-
uint32_t reserved3[256];
95+
/* Host mode register 0x0400 .. 0x07FF */
96+
volatile uint32_t hcfg;
97+
volatile uint32_t hfir;
98+
volatile uint32_t hfnum;
99+
volatile uint32_t reserved_0x40c[1];
100+
volatile uint32_t hptxsts;
101+
volatile uint32_t haint;
102+
volatile uint32_t haintmsk;
103+
volatile uint32_t hflbaddr;
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volatile uint32_t reserved_0x420_0x43c[8];
105+
volatile uint32_t hprt;
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volatile uint32_t reserved_0x0444_0x04fc[47];
107+
struct usb_dwc2_host_chan host_chan_regs[16];
108+
volatile uint32_t reserved_0x0704_0x07fc[64];
85109
/* Device mode register 0x0800 .. 0x0D00 */
86110
volatile uint32_t dcfg;
87111
volatile uint32_t dctl;
@@ -191,6 +215,17 @@ USB_DWC2_GET_FIELD_DEFINE(gahbcfg_hbstlen, GAHBCFG_HBSTLEN)
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#define USB_DWC2_GUSBCFG_FORCEDEVMODE BIT(USB_DWC2_GUSBCFG_FORCEDEVMODE_POS)
192216
#define USB_DWC2_GUSBCFG_FORCEHSTMODE_POS 29UL
193217
#define USB_DWC2_GUSBCFG_FORCEHSTMODE BIT(USB_DWC2_GUSBCFG_FORCEHSTMODE_POS)
218+
#define USB_DWC2_GUSBCFG_ULPIEVBUSD_POS 20UL
219+
#define USB_DWC2_GUSBCFG_ULPIEVBUSD BIT(USB_DWC2_GUSBCFG_ULPIEVBUSD_POS)
220+
#define USB_DWC2_GUSBCFG_ULPIEVBUSI_POS 21UL
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#define USB_DWC2_GUSBCFG_ULPIEVBUSI BIT(USB_DWC2_GUSBCFG_ULPIEVBUSI_POS)
222+
#define USB_DWC2_GUSBCFG_ULPICLK_SUSM_POS 19UL
223+
#define USB_DWC2_GUSBCFG_ULPICLK_SUSM BIT(USB_DWC2_GUSBCFG_ULPICLK_SUSM_POS)
224+
#define USB_DWC2_GUSBCFG_ULPIFSLS_POS 17UL
225+
#define USB_DWC2_GUSBCFG_ULPIFSLS BIT(USB_DWC2_GUSBCFG_ULPIFSLS_POS)
226+
#define USB_DWC2_GUSBCFG_DDR_SEL_POS 7UL
227+
#define USB_DWC2_GUSBCFG_DDR_SINGLE 0UL
228+
#define USB_DWC2_GUSBCFG_DDR_DOUBLE BIT(USB_DWC2_GUSBCFG_DDR_SEL_POS)
194229
#define USB_DWC2_GUSBCFG_PHYSEL_POS 6UL
195230
#define USB_DWC2_GUSBCFG_PHYSEL_USB11 BIT(USB_DWC2_GUSBCFG_PHYSEL_POS)
196231
#define USB_DWC2_GUSBCFG_PHYSEL_USB20 0UL
@@ -663,6 +698,163 @@ USB_DWC2_GET_FIELD_DEFINE(dieptxf_inepntxfstaddr, DIEPTXF_INEPNTXFSTADDR)
663698
USB_DWC2_SET_FIELD_DEFINE(dieptxf_inepntxfdep, DIEPTXF_INEPNTXFDEP)
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USB_DWC2_SET_FIELD_DEFINE(dieptxf_inepntxfstaddr, DIEPTXF_INEPNTXFSTADDR)
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701+
/* Periodic transmit FIFO size register (host mode) */
702+
#define USB_DWC2_HPTXFSIZ 0x0100UL
703+
#define USB_DWC2_HPTXFSIZ_PTXFSIZE_POS 16UL
704+
#define USB_DWC2_HPTXFSIZ_PTXFSIZE_MASK (0xFFFFUL << USB_DWC2_HPTXFSIZ_PTXFSIZE_POS)
705+
#define USB_DWC2_HPTXFSIZ_PTXFSTADDR_POS 0UL
706+
#define USB_DWC2_HPTXFSIZ_PTXFSTADDR_MASK (0xFFFFUL << USB_DWC2_HPTXFSIZ_PTXFSTADDR_POS)
707+
708+
709+
/* Host Configuration Register */
710+
#define USB_DWC2_HCFG 0x0400UL
711+
#define USB_DWC2_HCFG_MODECHTIMEN_POS 31UL
712+
#define USB_DWC2_HCFG_MODECHTIMEN BIT(USB_DWC2_HCFG_MODECHTIMEN_POS)
713+
#define USB_DWC2_HCFG_PERSCHEDENA_POS 26UL
714+
#define USB_DWC2_HCFG_PERSCHEDENA BIT(USB_DWC2_HCFG_PERSCHEDENA_POS)
715+
#define USB_DWC2_HCFG_FRLISTEN_POS 24UL
716+
#define USB_DWC2_HCFG_FRLISTEN_MASK (0x3UL << USB_DWC2_HCFG_FRLISTEN_POS)
717+
#define USB_DWC2_HCFG_DESCDMA_POS 23UL
718+
#define USB_DWC2_HCFG_DESCDMA BIT(USB_DWC2_HCFG_DESCDMA_POS)
719+
#define USB_DWC2_HCFG_DIS_TX_IPGAP_DLY_CHECK_POS 16UL
720+
#define USB_DWC2_HCFG_DIS_TX_IPGAP_DLY_CHECK BIT(USB_DWC2_HCFG_DIS_TX_IPGAP_DLY_CHECK_POS)
721+
#define USB_DWC2_HCFG_RESVALID_POS 8UL
722+
#define USB_DWC2_HCFG_RESVALID_MASK (0xFFUL << USB_DWC2_HCFG_RESVALID_POS)
723+
#define USB_DWC2_HCFG_ENA32KHZS_POS 7UL
724+
#define USB_DWC2_HCFG_ENA32KHZS BIT(USB_DWC2_HCFG_ENA32KHZS_POS)
725+
#define USB_DWC2_HCFG_FSLSSUPP_POS 2UL
726+
#define USB_DWC2_HCFG_FSLSSUPP BIT(USB_DWC2_HCFG_FSLSSUPP_POS)
727+
#define USB_DWC2_HCFG_FSLSPCLKSEL_POS 0UL
728+
#define USB_DWC2_HCFG_FSLSPCLKSEL_MASK (0x3UL << USB_DWC2_HCFG_FSLSPCLKSEL_POS)
729+
730+
USB_DWC2_SET_FIELD_DEFINE(hcfg_frlisten, HCFG_FRLISTEN)
731+
USB_DWC2_SET_FIELD_DEFINE(hcfg_resvalid, HCFG_RESVALID)
732+
USB_DWC2_SET_FIELD_DEFINE(hcfg_fslspclksel, HCFG_FSLSPCLKSEL)
733+
USB_DWC2_GET_FIELD_DEFINE(hcfg_frlisten, HCFG_FRLISTEN)
734+
USB_DWC2_GET_FIELD_DEFINE(hcfg_resvalid, HCFG_RESVALID)
735+
USB_DWC2_GET_FIELD_DEFINE(hcfg_fslspclksel, HCFG_FSLSPCLKSEL)
736+
737+
/* Host Frame Interval Register */
738+
#define USB_DWC2_HFIR 0x0404UL
739+
740+
#define USB_DWC2_HFIR_HFIRRLDCTRL_POS 16UL
741+
#define USB_DWC2_HFIR_HFIRRLDCTRL BIT(USB_DWC2_HFIR_HFIRRLDCTRL_POS)
742+
#define USB_DWC2_HFIR_FRINT_POS 0UL
743+
#define USB_DWC2_HFIR_FRINT_MASK (0xFFFFUL << USB_DWC2_HFIR_FRINT_POS)
744+
745+
USB_DWC2_SET_FIELD_DEFINE(hfir_frint, HFIR_FRINT)
746+
USB_DWC2_GET_FIELD_DEFINE(hfir_frint, HFIR_FRINT)
747+
748+
/* Host All Channels Interrupt Register */
749+
#define USB_DWC2_HAINT 0x0414UL
750+
#define USB_DWC2_HAINT_HAINT_POS 0UL
751+
#define USB_DWC2_HAINT_HAINT_MASK 0xFFFFUL /* Bits [15:0], 1 bit per host channel */
752+
753+
USB_DWC2_GET_FIELD_DEFINE(haint_haint, HAINT_HAINT)
754+
755+
/* Host Port Control and Status Register */
756+
#define USB_DWC2_HPRT 0x0440UL
757+
#define USB_DWC2_HPRT_PRTSPD_POS 17UL
758+
#define USB_DWC2_HPRT_PRTSPD_MASK (0x3UL << USB_DWC2_HPRT_PRTSPD_POS)
759+
#define USB_DWC2_HPRT_PRTTSTCTL_POS 13UL
760+
#define USB_DWC2_HPRT_PRTTSTCTL_MASK (0xFUL << USB_DWC2_HPRT_PRTTSTCTL_POS)
761+
#define USB_DWC2_HPRT_PRTLNSTS_POS 10UL
762+
#define USB_DWC2_HPRT_PRTLNSTS_MASK (0x3UL << USB_DWC2_HPRT_PRTLNSTS_POS)
763+
#define USB_DWC2_HPRT_PRTENA BIT(2)
764+
#define USB_DWC2_HPRT_PRTENCHNG BIT(3)
765+
#define USB_DWC2_HPRT_PRTOVRCURRACT BIT(4)
766+
#define USB_DWC2_HPRT_PRTOVRCURRCHNG BIT(5)
767+
#define USB_DWC2_HPRT_PRTRES BIT(6)
768+
#define USB_DWC2_HPRT_PRTSUSP BIT(7)
769+
#define USB_DWC2_HPRT_PRTRST BIT(8)
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#define USB_DWC2_HPRT_PRTCONNDET BIT(1)
771+
#define USB_DWC2_HPRT_PRTCONNSTS BIT(0)
772+
#define USB_DWC2_HPRT_PRTPWR BIT(12)
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#define USB_DWC2_HPRT_PRTSPD_HIGH 0
774+
#define USB_DWC2_HPRT_PRTSPD_FULL 1
775+
#define USB_DWC2_HPRT_PRTSPD_LOW 2
776+
777+
USB_DWC2_SET_FIELD_DEFINE(hprt_prtspd, HPRT_PRTSPD)
778+
USB_DWC2_SET_FIELD_DEFINE(hprt_prttstctl, HPRT_PRTTSTCTL)
779+
USB_DWC2_SET_FIELD_DEFINE(hprt_prtlnsts, HPRT_PRTLNSTS)
780+
USB_DWC2_GET_FIELD_DEFINE(hprt_prtspd, HPRT_PRTSPD)
781+
USB_DWC2_GET_FIELD_DEFINE(hprt_prttstctl, HPRT_PRTTSTCTL)
782+
USB_DWC2_GET_FIELD_DEFINE(hprt_prtlnsts, HPRT_PRTLNSTS)
783+
784+
/* Host Channel Characteristics Register (HCCHAR0) */
785+
#define USB_DWC2_HCCHAR0 0x0500UL
786+
787+
/* Bitfield Masks */
788+
#define USB_DWC2_HCCHAR0_CHENA BIT(31)
789+
#define USB_DWC2_HCCHAR0_CHDIS BIT(30)
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#define USB_DWC2_HCCHAR0_ODDFRM BIT(29)
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#define USB_DWC2_HCCHAR0_DEVADDR_POS 22UL
792+
#define USB_DWC2_HCCHAR0_DEVADDR_MASK (0x7FUL << USB_DWC2_HCCHAR0_DEVADDR_POS)
793+
#define USB_DWC2_HCCHAR0_EC_POS 20UL
794+
#define USB_DWC2_HCCHAR0_EC_MASK (0x3UL << USB_DWC2_HCCHAR0_EC_POS)
795+
#define USB_DWC2_HCCHAR0_EPTYPE_POS 18UL
796+
#define USB_DWC2_HCCHAR0_EPTYPE_MASK (0x3UL << USB_DWC2_HCCHAR0_EPTYPE_POS)
797+
#define USB_DWC2_HCCHAR0_LSPDDEV BIT(17)
798+
#define USB_DWC2_HCCHAR0_EPDIR BIT(15)
799+
#define USB_DWC2_HCCHAR0_EPNUM_POS 11UL
800+
#define USB_DWC2_HCCHAR0_EPNUM_MASK (0xFUL << USB_DWC2_HCCHAR0_EPNUM_POS)
801+
#define USB_DWC2_HCCHAR0_MPS_POS 0UL
802+
#define USB_DWC2_HCCHAR0_MPS_MASK (0x7FFUL << USB_DWC2_HCCHAR0_MPS_POS)
803+
804+
USB_DWC2_SET_FIELD_DEFINE(hcchar0_devaddr, HCCHAR0_DEVADDR)
805+
USB_DWC2_SET_FIELD_DEFINE(hcchar0_ec, HCCHAR0_EC)
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USB_DWC2_SET_FIELD_DEFINE(hcchar0_eptype, HCCHAR0_EPTYPE)
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USB_DWC2_SET_FIELD_DEFINE(hcchar0_epnum, HCCHAR0_EPNUM)
808+
USB_DWC2_SET_FIELD_DEFINE(hcchar0_mps, HCCHAR0_MPS)
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USB_DWC2_GET_FIELD_DEFINE(hcchar0_devaddr, HCCHAR0_DEVADDR)
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USB_DWC2_GET_FIELD_DEFINE(hcchar0_ec, HCCHAR0_EC)
811+
USB_DWC2_GET_FIELD_DEFINE(hcchar0_eptype, HCCHAR0_EPTYPE)
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USB_DWC2_GET_FIELD_DEFINE(hcchar0_epnum, HCCHAR0_EPNUM)
813+
USB_DWC2_GET_FIELD_DEFINE(hcchar0_mps, HCCHAR0_MPS)
814+
815+
/*
816+
* Host Channel Interrupt Mask Registers (HCINTMSK)
817+
* Offset: 0x050C + (0x20 * i), i = 0 .. (OTG_NUM_HOST_CHAN - 1)
818+
*/
819+
#define USB_DWC2_HCINT0 0x0508UL
820+
#define USB_DWC2_HCINTMSK0 0x050CUL
821+
#define USB_DWC2_HCINT_XFERCOMPL BIT(0)
822+
#define USB_DWC2_HCINT_CHHLTD BIT(1)
823+
#define USB_DWC2_HCINT_AHBERR BIT(2)
824+
#define USB_DWC2_HCINT_STALL BIT(3)
825+
#define USB_DWC2_HCINT_NAK BIT(4)
826+
#define USB_DWC2_HCINT_ACK BIT(5)
827+
#define USB_DWC2_HCINT_NYET BIT(6)
828+
#define USB_DWC2_HCINT_XACTERR BIT(7)
829+
#define USB_DWC2_HCINT_BBLERR BIT(8)
830+
#define USB_DWC2_HCINT_FRMOVRUN BIT(9)
831+
#define USB_DWC2_HCINT_DTGERR BIT(10)
832+
#define USB_DWC2_HCINT_BNA BIT(11)
833+
#define USB_DWC2_HCINT_DESC_LST_ROLL BIT(13)
834+
835+
/* Host Channel Transfer Size Register */
836+
#define USB_DWC2_HCTSIZ0 0x0510UL
837+
#define USB_DWC2_HCTSIZ_XFERSIZE_POS 0UL
838+
#define USB_DWC2_HCTSIZ_XFERSIZE_MASK (0x7FFFFUL << USB_DWC2_HCTSIZ_XFERSIZE_POS)
839+
#define USB_DWC2_HCTSIZ_PKTCNT_POS 19UL
840+
#define USB_DWC2_HCTSIZ_PKTCNT_MASK (0x3FFUL << USB_DWC2_HCTSIZ_PKTCNT_POS)
841+
#define USB_DWC2_HCTSIZ_PID_POS 29UL
842+
#define USB_DWC2_HCTSIZ_PID_MASK (0x3UL << USB_DWC2_HCTSIZ_PID_POS)
843+
#define USB_DWC2_HCTSIZ_DOPNG BIT(31)
844+
845+
USB_DWC2_SET_FIELD_DEFINE(hctsiz_xfersize, HCTSIZ_XFERSIZE)
846+
USB_DWC2_SET_FIELD_DEFINE(hctsiz_pktcnt, HCTSIZ_PKTCNT)
847+
USB_DWC2_SET_FIELD_DEFINE(hctsiz_pid, HCTSIZ_PID)
848+
USB_DWC2_GET_FIELD_DEFINE(hctsiz_xfersize, HCTSIZ_XFERSIZE)
849+
USB_DWC2_GET_FIELD_DEFINE(hctsiz_pktcnt, HCTSIZ_PKTCNT)
850+
USB_DWC2_GET_FIELD_DEFINE(hctsiz_pid, HCTSIZ_PID)
851+
852+
/* Host Channel DMA Address Register */
853+
#define USB_DWC2_HCDMA0 0x0514UL
854+
855+
/* Host Channel DMA Buffer Address Register */
856+
#define USB_DWC2_HCDMAB0 0x051CUL
857+
666858
/* Device configuration registers */
667859
#define USB_DWC2_DCFG 0x0800UL
668860
#define USB_DWC2_DCFG_RESVALID_POS 26UL

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