soc: nrf53: Add configuration options for HFXO/LFXO load capacitance

Add Kconfig options that allow configuration of optional internal
load capacitors for the high-frequency (HFXO) and low-frequency
(LFXO) crystal oscillators in nRF5340.
Default settings used for the new options are those that have been
in effect so far, i.e. external load capacitors for HFXO and 6 pF
internal capacitance for LFXO.

This commit also adds missing SOC_ENABLE_LFXO option dependency on
!TRUSTED_EXECUTION_NONSECURE.

Signed-off-by: Andrzej Głąbek <[email protected]>

Author: anangl

soc/arm/nordic_nrf/nrf53/Kconfig.soc

@@ -132,6 +132,8 @@ config SOC_DCDC_NRF53X_HV
 	help
 	  Enable nRF53 series System on Chip High Voltage DC/DC converter.
 
+if !TRUSTED_EXECUTION_NONSECURE
+
 config SOC_ENABLE_LFXO
 	bool "Enable LFXO"
 	default y
@@ -142,6 +144,49 @@ config SOC_ENABLE_LFXO
 	  to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular
 	  GPIOs.
 
+choice SOC_LFXO_LOAD_CAPACITANCE
+	prompt "LFXO load capacitance"
+	depends on SOC_ENABLE_LFXO
+	default SOC_LFXO_CAP_INT_6PF
+
+config SOC_LFXO_CAP_EXTERNAL
+	bool "Use external load capacitors"
+
+config SOC_LFXO_CAP_INT_6PF
+	bool "6 pF internal load capacitance"
+
+config SOC_LFXO_CAP_INT_7PF
+	bool "7 pF internal load capacitance"
+
+config SOC_LFXO_CAP_INT_9PF
+	bool "9 pF internal load capacitance"
+
+endchoice
+
+choice SOC_HFXO_LOAD_CAPACITANCE
+	prompt "HFXO load capacitance"
+	default SOC_HFXO_CAP_EXTERNAL
+
+config SOC_HFXO_CAP_EXTERNAL
+	bool "Use external load capacitors"
+
+config SOC_HFXO_CAP_INTERNAL
+	bool "Use internal load capacitors"
+
+endchoice
+
+config SOC_HFXO_CAP_INT_VALUE_X2
+	int "Doubled value of HFXO internal load capacitors (in pF)"
+	depends on SOC_HFXO_CAP_INTERNAL
+	range 14 40
+	help
+	  Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps
+	  can be enabled on pins XC1 and XC2. This option specifies doubled
+	  capacitance value for the two capacitors. Set it to 14 to get 7.0 pF
+	  for each capacitor, 15 to get 7.5 pF, and so on.
+
+endif # !TRUSTED_EXECUTION_NONSECURE
+
 endif # SOC_NRF5340_CPUAPP
 
 

soc/arm/nordic_nrf/nrf53/soc.c

@@ -64,13 +64,42 @@ static int nordicsemi_nrf53_init(const struct device *arg)
 #endif
 
 #if defined(CONFIG_SOC_NRF5340_CPUAPP) && \
-	!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) && \
-	defined(CONFIG_SOC_ENABLE_LFXO)
+	!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
+#if defined(CONFIG_SOC_ENABLE_LFXO)
 	nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS,
-				     NRF_OSCILLATORS_LFXO_CAP_6PF);
+		IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_6PF) ?
+			NRF_OSCILLATORS_LFXO_CAP_6PF :
+		IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_7PF) ?
+			NRF_OSCILLATORS_LFXO_CAP_7PF :
+		IS_ENABLED(CONFIG_SOC_LFXO_CAP_INT_9PF) ?
+			NRF_OSCILLATORS_LFXO_CAP_9PF :
+			NRF_OSCILLATORS_LFXO_CAP_EXTERNAL);
+	/* This can only be done from secure code. */
 	nrf_gpio_pin_mcu_select(PIN_XL1, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
 	nrf_gpio_pin_mcu_select(PIN_XL2, NRF_GPIO_PIN_MCUSEL_PERIPHERAL);
 #endif
+#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
+	/* This register is only accessible from secure code. */
+	uint32_t xosc32mtrim = NRF_FICR->XOSC32MTRIM;
+	/* As specified in the nRF5340 PS:
+	 * CAPVALUE = (((FICR->XOSC32MTRIM.SLOPE+56)*(CAPACITANCE*2-14))
+	 *            +((FICR->XOSC32MTRIM.OFFSET-8)<<4)+32)>>6;
+	 * where CAPACITANCE is the desired capacitor value in pF, holding any
+	 * value between 7.0 pF and 20.0 pF in 0.5 pF steps.
+	 */
+	uint32_t slope = (xosc32mtrim & FICR_XOSC32MTRIM_SLOPE_Msk)
+			 >> FICR_XOSC32MTRIM_SLOPE_Pos;
+	uint32_t offset = (xosc32mtrim & FICR_XOSC32MTRIM_OFFSET_Msk)
+			  >> FICR_XOSC32MTRIM_OFFSET_Pos;
+	uint32_t capvalue =
+		((slope + 56) * (CONFIG_SOC_HFXO_CAP_INT_VALUE_X2 - 14)
+		 + ((offset - 8) << 4) + 32) >> 6;
+
+	nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, true, capvalue);
+#else
+	nrf_oscillators_hfxo_cap_set(NRF_OSCILLATORS, false, 0);
+#endif
+#endif /* defined(CONFIG_SOC_NRF5340_CPUAPP) && ... */
 
 #if defined(CONFIG_SOC_DCDC_NRF53X_APP)
 	nrf_regulators_dcdcen_set(NRF_REGULATORS, true);