@@ -88,6 +88,27 @@ static int frdm_mcxn236_init(void)
8888 /* Set AHBCLKDIV divider to value 1 */
8989 CLOCK_SetClkDiv (kCLOCK_DivAhbClk , 1U );
9090
91+ CLOCK_SetupExtClocking (BOARD_XTAL0_CLK_HZ );
92+
93+ #if DT_NODE_HAS_STATUS_OKAY (DT_NODELABEL (flexcan1 ))
94+ /* Set up PLL1 for 80 MHz FlexCAN clock */
95+ const pll_setup_t pll1Setup = {
96+ .pllctrl = SCG_SPLLCTRL_SOURCE (1U ) | SCG_SPLLCTRL_SELI (27U ) |
97+ SCG_SPLLCTRL_SELP (13U ),
98+ .pllndiv = SCG_SPLLNDIV_NDIV (3U ),
99+ .pllpdiv = SCG_SPLLPDIV_PDIV (1U ),
100+ .pllmdiv = SCG_SPLLMDIV_MDIV (10U ),
101+ .pllRate = 80000000U
102+ };
103+
104+ /* Configure PLL1 to the desired values */
105+ CLOCK_SetPLL1Freq (& pll1Setup );
106+ /* PLL1 Monitor is disabled */
107+ CLOCK_SetPll1MonitorMode (kSCG_Pll1MonitorDisable );
108+ /* Set PLL1 CLK0 divider to value 1 */
109+ CLOCK_SetClkDiv (kCLOCK_DivPLL1Clk0 , 1U );
110+ #endif
111+
91112#if DT_NODE_HAS_STATUS_OKAY (DT_NODELABEL (flexcomm1 ))
92113 CLOCK_SetClkDiv (kCLOCK_DivFlexcom1Clk , 1u );
93114 CLOCK_AttachClk (kFRO12M_to_FLEXCOMM1 );
@@ -170,6 +191,11 @@ static int frdm_mcxn236_init(void)
170191 CLOCK_AttachClk (kPLL0_to_CTIMER4 );
171192#endif
172193
194+ #if DT_NODE_HAS_STATUS_OKAY (DT_NODELABEL (flexcan1 ))
195+ CLOCK_SetClkDiv (kCLOCK_DivFlexcan1Clk , 1U );
196+ CLOCK_AttachClk (kPLL1_CLK0_to_FLEXCAN1 );
197+ #endif
198+
173199#if DT_NODE_HAS_STATUS_OKAY (DT_NODELABEL (vref ))
174200 CLOCK_EnableClock (kCLOCK_Vref );
175201 SPC_EnableActiveModeAnalogModules (SPC0 , kSPC_controlVref );
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