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FRASTMMaureenHelm
FRASTM
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MaureenHelm
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drivers: clock_control: Add STM32G0XX clock support
Add clock support for STM32G0X SoC series. Signed-off-by: Philippe Retornaz <[email protected] Signed-off-by: Francois Ramu <[email protected]>
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6 files changed

+129
-18
lines changed

6 files changed

+129
-18
lines changed

‎drivers/clock_control/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ else()
2222
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F3X clock_stm32f0_f3.c)
2323
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X clock_stm32f2_f4_f7.c)
2424
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X clock_stm32f2_f4_f7.c)
25+
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X clock_stm32g0.c)
2526
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L0X clock_stm32l0_l1.c)
2627
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c)
2728
zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_wb.c)

‎drivers/clock_control/Kconfig.stm32‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ source "drivers/clock_control/Kconfig.stm32f2_f4_f7"
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source "drivers/clock_control/Kconfig.stm32h7"
126126
source "drivers/clock_control/Kconfig.stm32l0_l1"
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source "drivers/clock_control/Kconfig.stm32l4_wb"
128-
128+
source "drivers/clock_control/Kconfig.stm32g0"
129129

130130
# Bus clocks configuration options
131131

‎drivers/clock_control/Kconfig.stm32g0‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
# Kconfig - STM32G0 PLL configuration options
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#
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# Copyright (c) 2019 Linaro
4+
#
5+
# SPDX-License-Identifier: Apache-2.0
6+
#
7+
8+
if SOC_SERIES_STM32G0X
9+
10+
config CLOCK_STM32_PLL_N_MULTIPLIER
11+
int "PLL multiplier"
12+
depends on CLOCK_STM32_SYSCLK_SRC_PLL
13+
default 8
14+
range 8 86
15+
help
16+
PLL multiplier, allowed values: 8-86
17+
PLL output must not exceed 56MHz(1.8V)/26MHz(1.2V).
18+
19+
config CLOCK_STM32_PLL_M_DIVISOR
20+
int "PLL divisor"
21+
depends on CLOCK_STM32_SYSCLK_SRC_PLL
22+
default 1
23+
range 1 8
24+
help
25+
PLL divisor, allowed values: 1-8.
26+
27+
config CLOCK_STM32_PLL_P_DIVISOR
28+
int "PLL P Divisor"
29+
depends on CLOCK_STM32_SYSCLK_SRC_PLL
30+
default 2
31+
range 2 32
32+
help
33+
PLL P VCO divisor, allowed values: 2-32.
34+
35+
config CLOCK_STM32_PLL_Q_DIVISOR
36+
int "PLL Q Divisor"
37+
depends on CLOCK_STM32_SYSCLK_SRC_PLL
38+
default 2
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range 2 8
40+
help
41+
PLL Q VCO divisor, allowed values: 2-8.
42+
43+
config CLOCK_STM32_PLL_R_DIVISOR
44+
int "PLL R Divisor"
45+
depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
47+
range 2 8
48+
help
49+
PLL R VCO divisor, allowed values: 2-8.
50+
51+
endif # SOC_SERIES_STM32G0X

‎drivers/clock_control/clock_stm32_ll_common.c‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -54,10 +54,10 @@ static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
5454
clk_init->APB1CLKDivider = apb1_prescaler(
5555
CONFIG_CLOCK_STM32_APB1_PRESCALER);
5656

57-
#ifndef CONFIG_SOC_SERIES_STM32F0X
57+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
5858
clk_init->APB2CLKDivider = apb2_prescaler(
5959
CONFIG_CLOCK_STM32_APB2_PRESCALER);
60-
#endif /* CONFIG_SOC_SERIES_STM32F0X */
60+
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
6161
}
6262

6363
static u32_t get_bus_clock(u32_t clock, u32_t prescaler)
@@ -96,16 +96,16 @@ static inline int stm32_clock_control_on(struct device *dev,
9696
LL_APB1_GRP2_EnableClock(pclken->enr);
9797
break;
9898
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
99-
#ifndef CONFIG_SOC_SERIES_STM32F0X
99+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
100100
case STM32_CLOCK_BUS_APB2:
101101
LL_APB2_GRP1_EnableClock(pclken->enr);
102102
break;
103-
#endif /* CONFIG_SOC_SERIES_STM32F0X */
104-
#ifdef CONFIG_SOC_SERIES_STM32L0X
103+
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
104+
#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X)
105105
case STM32_CLOCK_BUS_IOP:
106106
LL_IOP_GRP1_EnableClock(pclken->enr);
107107
break;
108-
#endif /* CONFIG_SOC_SERIES_STM32L0X */
108+
#endif /* CONFIG_SOC_SERIES_STM32L0X || CONFIG_SOC_SERIES_STM32G0X */
109109
default:
110110
return -ENOTSUP;
111111
}
@@ -144,11 +144,11 @@ static inline int stm32_clock_control_off(struct device *dev,
144144
LL_APB1_GRP2_DisableClock(pclken->enr);
145145
break;
146146
#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
147-
#ifndef CONFIG_SOC_SERIES_STM32F0X
147+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
148148
case STM32_CLOCK_BUS_APB2:
149149
LL_APB2_GRP1_DisableClock(pclken->enr);
150150
break;
151-
#endif /* CONFIG_SOC_SERIES_STM32F0X */
151+
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
152152
#ifdef CONFIG_SOC_SERIES_STM32L0X
153153
case STM32_CLOCK_BUS_IOP:
154154
LL_IOP_GRP1_DisableClock(pclken->enr);
@@ -176,10 +176,10 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
176176
u32_t ahb_clock = SystemCoreClock;
177177
u32_t apb1_clock = get_bus_clock(ahb_clock,
178178
CONFIG_CLOCK_STM32_APB1_PRESCALER);
179-
#ifndef CONFIG_SOC_SERIES_STM32F0X
179+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
180180
u32_t apb2_clock = get_bus_clock(ahb_clock,
181181
CONFIG_CLOCK_STM32_APB2_PRESCALER);
182-
#endif /* CONFIG_SOC_SERIES_STM32F0X */
182+
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
183183

184184
ARG_UNUSED(clock);
185185

@@ -199,11 +199,11 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
199199
#endif
200200
*rate = apb1_clock;
201201
break;
202-
#ifndef CONFIG_SOC_SERIES_STM32F0X
202+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
203203
case STM32_CLOCK_BUS_APB2:
204204
*rate = apb2_clock;
205205
break;
206-
#endif /* CONFIG_SOC_SERIES_STM32F0X */
206+
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
207207
default:
208208
return -ENOTSUP;
209209
}
@@ -376,9 +376,9 @@ static int stm32_clock_control_init(struct device *dev)
376376

377377
/* Set APB1 & APB2 prescaler*/
378378
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
379-
#ifndef CONFIG_SOC_SERIES_STM32F0X
379+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
380380
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
381-
#endif /* CONFIG_SOC_SERIES_STM32F0X */
381+
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
382382

383383
/* Set flash latency */
384384
/* HSI used as SYSCLK, set latency to 0 */
@@ -447,9 +447,9 @@ static int stm32_clock_control_init(struct device *dev)
447447

448448
/* Set APB1 & APB2 prescaler*/
449449
LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider);
450-
#ifndef CONFIG_SOC_SERIES_STM32F0X
450+
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
451451
LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider);
452-
#endif /* CONFIG_SOC_SERIES_STM32F0X */
452+
#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */
453453

454454
/* Set flash latency */
455455
/* HSI used as SYSCLK, set latency to 0 */

‎drivers/clock_control/clock_stm32g0.c‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
/*
2+
*
3+
* Copyright (c) 2019 Ilya Tagunov
4+
* Copyright (c) 2019 STMicroelectronics
5+
*
6+
* SPDX-License-Identifier: Apache-2.0
7+
*/
8+
9+
10+
#include <soc.h>
11+
#include <clock_control.h>
12+
#include <misc/util.h>
13+
#include <clock_control/stm32_clock_control.h>
14+
#include "clock_stm32_ll_common.h"
15+
16+
17+
#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
18+
19+
/* Macros to fill up multiplication and division factors values */
20+
#define z_pll_div(v) LL_RCC_PLLM_DIV_ ## v
21+
#define pll_div(v) z_pll_div(v)
22+
23+
#define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
24+
#define pllr(v) z_pllr(v)
25+
26+
/**
27+
* @brief Fill PLL configuration structure
28+
*/
29+
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
30+
{
31+
pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
32+
pllinit->PLLM = pll_div(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
33+
pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
34+
}
35+
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
36+
37+
/**
38+
* @brief Activate default clocks
39+
*/
40+
void config_enable_default_clocks(void)
41+
{
42+
/* Do nothing */
43+
}
44+
45+
/**
46+
* @brief Function kept for driver genericity
47+
*/
48+
void LL_RCC_MSI_Disable(void)
49+
{
50+
/* Do nothing */
51+
}

‎dts/arm/st/g0/stm32g0.dtsi‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,17 @@
4646
};
4747
};
4848

49+
rcc: rcc@40021000 {
50+
compatible = "st,stm32-rcc";
51+
clocks-controller;
52+
#clock-cells = <2>;
53+
reg = <0x40021000 0x400>;
54+
label = "STM32_CLK_RCC";
55+
};
56+
4957
};
5058
};
5159

5260
&nvic {
5361
arm,num-irq-priority-bits = <2>;
54-
};
62+
};

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