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drivers: adc: stm32: Rename sequencer and oversampler and fix macro issue
In STM32 ADC binding, rename the possible values of the sequencer and oversampler properties to use lowercase string, similar to the internal regulator. Adapts the driver and the dtsi with the new values. Fixes a macro issue in the driver. Since the value from the dtsi didn't start with internal_regulator_, the reconstruction of the defines by the macro ANY_ADC_INTERNAL_REGULATOR_TYPE_IS was missing this prefix and the comparison failed. Add a new argument to the IS_EQ_STRING_PROP to be able to insert such a prefix. Signed-off-by: Guillaume Gautier <[email protected]>
1 parent 7920c38 commit 625e2ac

37 files changed

+136
-134
lines changed

‎drivers/adc/adc_stm32.c‎

Lines changed: 21 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -86,8 +86,8 @@ LOG_MODULE_REGISTER(adc_stm32);
8686
#define ASYNC 2
8787

8888
/* Sequencer type */
89-
#define NOT_FULLY_CONFIGURABLE 0
90-
#define FULLY_CONFIGURABLE 1
89+
#define SEQUENCER_FIXED 0
90+
#define SEQUENCER_PROGRAMMABLE 1
9191

9292
/* Oversampler type */
9393
#define OVERSAMPLER_NONE 0
@@ -107,17 +107,17 @@ LOG_MODULE_REGISTER(adc_stm32);
107107
#define ANY_ADC_SEQUENCER_TYPE_IS(value) \
108108
(DT_INST_FOREACH_STATUS_OKAY_VARGS(IS_EQ_STRING_PROP, \
109109
st_adc_sequencer,\
110-
value) 0)
110+
value, SEQUENCER_) 0)
111111

112112
#define ANY_ADC_OVERSAMPLER_TYPE_IS(value) \
113113
(DT_INST_FOREACH_STATUS_OKAY_VARGS(IS_EQ_STRING_PROP, \
114114
st_adc_oversampler,\
115-
value) 0)
115+
value, OVERSAMPLER_) 0)
116116

117117
#define ANY_ADC_INTERNAL_REGULATOR_TYPE_IS(value) \
118118
(DT_INST_FOREACH_STATUS_OKAY_VARGS(IS_EQ_STRING_PROP, \
119119
st_adc_internal_regulator,\
120-
value) 0)
120+
value, INTERNAL_REGULATOR_) 0)
121121

122122
#define ANY_ADC_HAS_DEEP_POWERDOWN \
123123
(DT_INST_FOREACH_STATUS_OKAY_VARGS(IS_EQ_PROP_OR, \
@@ -145,13 +145,13 @@ LOG_MODULE_REGISTER(adc_stm32);
145145
#define IS_EQ_NODE_PROP_OR(node, prop, default_value, compare_value) \
146146
IS_EQ(DT_PROP_OR(node, prop, default_value), compare_value) ||
147147

148-
#define IS_EQ_STRING_PROP(inst, prop, compare_value) \
149-
IS_EQ(DT_INST_STRING_UPPER_TOKEN(inst, prop), compare_value) ||
148+
#define IS_EQ_STRING_PROP(inst, prop, compare_value, prefix) \
149+
IS_EQ(CONCAT(prefix, DT_INST_STRING_UPPER_TOKEN(inst, prop)), compare_value) ||
150150

151151
/* reference voltage for the ADC */
152152
#define STM32_ADC_VREF_MV DT_INST_PROP(0, vref_mv)
153153

154-
#if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
154+
#if ANY_ADC_SEQUENCER_TYPE_IS(SEQUENCER_PROGRAMMABLE)
155155

156156
#if defined(LL_ADC_REG_RANK_28)
157157
#define MAX_RANK 28
@@ -172,7 +172,7 @@ static const uint32_t table_seq_len[] = {
172172
LISTIFY(UTIL_DEC(MAX_RANK), SEQ_LEN, (,))
173173
};
174174

175-
#endif /* ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE) */
175+
#endif /* ANY_ADC_SEQUENCER_TYPE_IS(SEQUENCER_PROGRAMMABLE) */
176176

177177
/* Number of different sampling time values */
178178
#define STM32_NB_SAMPLING_TIME 8
@@ -946,8 +946,8 @@ static int set_sequencer(const struct device *dev)
946946

947947
channels_mask |= channel;
948948

949-
#if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
950-
if (config->sequencer_type == FULLY_CONFIGURABLE) {
949+
#if ANY_ADC_SEQUENCER_TYPE_IS(SEQUENCER_PROGRAMMABLE)
950+
if (config->sequencer_type == SEQUENCER_PROGRAMMABLE) {
951951
#if ANY_ADC_HAS_CHANNEL_PRESELECTION
952952
if (config->has_channel_preselection) {
953953
/*
@@ -961,11 +961,11 @@ static int set_sequencer(const struct device *dev)
961961
LL_ADC_REG_SetSequencerRanks(adc, table_rank[channel_index], channel);
962962
LL_ADC_REG_SetSequencerLength(adc, table_seq_len[channel_index]);
963963
}
964-
#endif /* ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE) */
964+
#endif /* ANY_ADC_SEQUENCER_TYPE_IS(SEQUENCER_PROGRAMMABLE) */
965965
}
966966

967-
#if ANY_ADC_SEQUENCER_TYPE_IS(NOT_FULLY_CONFIGURABLE)
968-
if (config->sequencer_type == NOT_FULLY_CONFIGURABLE) {
967+
#if ANY_ADC_SEQUENCER_TYPE_IS(SEQUENCER_FIXED)
968+
if (config->sequencer_type == SEQUENCER_FIXED) {
969969
LL_ADC_REG_SetSequencerChannels(adc, channels_mask);
970970

971971
#ifdef LL_ADC_FLAG_CCRDY
@@ -978,7 +978,7 @@ static int set_sequencer(const struct device *dev)
978978
LL_ADC_ClearFlag_CCRDY(adc);
979979
#endif /* LL_ADC_FLAG_CCRDY */
980980
}
981-
#endif /* ANY_ADC_SEQUENCER_TYPE_IS(NOT_FULLY_CONFIGURABLE) */
981+
#endif /* ANY_ADC_SEQUENCER_TYPE_IS(SEQUENCER_FIXED) */
982982

983983
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) || \
984984
DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
@@ -1006,12 +1006,12 @@ static int start_read(const struct device *dev,
10061006
return -EINVAL;
10071007
}
10081008

1009-
#if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
1009+
#if ANY_ADC_SEQUENCER_TYPE_IS(SEQUENCER_PROGRAMMABLE)
10101010
if (data->channel_count > ARRAY_SIZE(table_seq_len)) {
10111011
LOG_ERR("Too many channels for sequencer. Max: %d", ARRAY_SIZE(table_seq_len));
10121012
return -EINVAL;
10131013
}
1014-
#endif /* ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE) */
1014+
#endif /* ANY_ADC_SEQUENCER_TYPE_IS(SEQUENCER_PROGRAMMABLE) */
10151015

10161016
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && !defined(CONFIG_ADC_STM32_DMA)
10171017
/* Multiple samplings is only supported with DMA for F1 */
@@ -1974,8 +1974,10 @@ static const struct adc_stm32_cfg adc_stm32_cfg_##index = { \
19741974
.clk_prescaler = ADC_STM32_DT_PRESC(index), \
19751975
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
19761976
.differential_channels_used = (ANY_CHILD_NODE_IS_DIFFERENTIAL(index) > 0), \
1977-
.sequencer_type = DT_INST_STRING_UPPER_TOKEN(index, st_adc_sequencer), \
1978-
.oversampler_type = DT_INST_STRING_UPPER_TOKEN(index, st_adc_oversampler), \
1977+
.sequencer_type = CONCAT(SEQUENCER_, \
1978+
DT_INST_STRING_UPPER_TOKEN(index, st_adc_sequencer)), \
1979+
.oversampler_type = CONCAT(OVERSAMPLER_, \
1980+
DT_INST_STRING_UPPER_TOKEN(index, st_adc_oversampler)), \
19791981
.internal_regulator = CONCAT(INTERNAL_REGULATOR_, \
19801982
DT_INST_STRING_UPPER_TOKEN(index, st_adc_internal_regulator)), \
19811983
.has_deep_powerdown = DT_INST_PROP(index, st_adc_has_deep_powerdown), \

‎dts/arm/st/c0/stm32c0.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -466,8 +466,8 @@
466466
STM32_ADC_RES(6, 0x03)>;
467467
sampling-times = <2 4 8 13 20 40 80 161>;
468468
num-sampling-time-common-channels = <2>;
469-
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
470-
st,adc-oversampler = "OVERSAMPLER_MINIMAL";
469+
st,adc-sequencer = "fixed";
470+
st,adc-oversampler = "minimal";
471471
st,adc-internal-regulator = "startup-sw-delay";
472472
status = "disabled";
473473
};

‎dts/arm/st/f0/stm32f0.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -354,8 +354,8 @@
354354
STM32_ADC_RES(6, 0x03)>;
355355
sampling-times = <2 8 14 29 42 56 72 240>;
356356
num-sampling-time-common-channels = <1>;
357-
st,adc-sequencer = "NOT_FULLY_CONFIGURABLE";
358-
st,adc-oversampler = "OVERSAMPLER_NONE";
357+
st,adc-sequencer = "fixed";
358+
st,adc-oversampler = "none";
359359
st,adc-internal-regulator = "none";
360360
status = "disabled";
361361
};

‎dts/arm/st/f1/stm32f1.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -397,8 +397,8 @@
397397
#io-channel-cells = <1>;
398398
resolutions = <STM32F1_ADC_RES(12)>;
399399
sampling-times = <2 8 14 29 42 56 72 240>;
400-
st,adc-sequencer = "FULLY_CONFIGURABLE";
401-
st,adc-oversampler = "OVERSAMPLER_NONE";
400+
st,adc-sequencer = "programmable";
401+
st,adc-oversampler = "none";
402402
st,adc-internal-regulator = "none";
403403
status = "disabled";
404404
};

‎dts/arm/st/f1/stm32f103Xc.dtsi‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -137,8 +137,8 @@
137137
#io-channel-cells = <1>;
138138
resolutions = <STM32F1_ADC_RES(12)>;
139139
sampling-times = <2 8 14 29 42 56 72 240>;
140-
st,adc-sequencer = "FULLY_CONFIGURABLE";
141-
st,adc-oversampler = "OVERSAMPLER_NONE";
140+
st,adc-sequencer = "programmable";
141+
st,adc-oversampler = "none";
142142
st,adc-internal-regulator = "none";
143143
status = "disabled";
144144
};
@@ -151,8 +151,8 @@
151151
#io-channel-cells = <1>;
152152
resolutions = <STM32F1_ADC_RES(12)>;
153153
sampling-times = <2 8 14 29 42 56 72 240>;
154-
st,adc-sequencer = "FULLY_CONFIGURABLE";
155-
st,adc-oversampler = "OVERSAMPLER_NONE";
154+
st,adc-sequencer = "programmable";
155+
st,adc-oversampler = "none";
156156
st,adc-internal-regulator = "none";
157157
status = "disabled";
158158
};

‎dts/arm/st/f2/stm32f2.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -377,8 +377,8 @@
377377
STM32_ADC_RES(6, 0x03)>;
378378
sampling-times = <3 15 28 58 84 112 144 480>;
379379
st,adc-clock-source = "SYNC";
380-
st,adc-sequencer = "FULLY_CONFIGURABLE";
381-
st,adc-oversampler = "OVERSAMPLER_NONE";
380+
st,adc-sequencer = "programmable";
381+
st,adc-oversampler = "none";
382382
st,adc-internal-regulator = "none";
383383
status = "disabled";
384384
};

‎dts/arm/st/f3/stm32f302.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -118,8 +118,8 @@
118118
STM32_ADC_RES(8, 0x02)
119119
STM32_ADC_RES(6, 0x03)>;
120120
sampling-times = <2 3 5 8 20 62 182 602>;
121-
st,adc-sequencer = "FULLY_CONFIGURABLE";
122-
st,adc-oversampler = "OVERSAMPLER_NONE";
121+
st,adc-sequencer = "programmable";
122+
st,adc-oversampler = "none";
123123
st,adc-internal-regulator = "startup-sw-delay";
124124
st,adc-has-differential-support;
125125
status = "disabled";

‎dts/arm/st/f3/stm32f303.dtsi‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -154,8 +154,8 @@
154154
STM32_ADC_RES(8, 0x02)
155155
STM32_ADC_RES(6, 0x03)>;
156156
sampling-times = <2 3 5 8 20 62 182 602>;
157-
st,adc-sequencer = "FULLY_CONFIGURABLE";
158-
st,adc-oversampler = "OVERSAMPLER_NONE";
157+
st,adc-sequencer = "programmable";
158+
st,adc-oversampler = "none";
159159
st,adc-internal-regulator = "startup-sw-delay";
160160
st,adc-has-differential-support;
161161
status = "disabled";
@@ -173,8 +173,8 @@
173173
STM32_ADC_RES(8, 0x02)
174174
STM32_ADC_RES(6, 0x03)>;
175175
sampling-times = <2 3 5 8 20 62 182 602>;
176-
st,adc-sequencer = "FULLY_CONFIGURABLE";
177-
st,adc-oversampler = "OVERSAMPLER_NONE";
176+
st,adc-sequencer = "programmable";
177+
st,adc-oversampler = "none";
178178
st,adc-internal-regulator = "startup-sw-delay";
179179
st,adc-has-differential-support;
180180
status = "disabled";

‎dts/arm/st/f3/stm32f334.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -93,8 +93,8 @@
9393
STM32_ADC_RES(8, 0x02)
9494
STM32_ADC_RES(6, 0x03)>;
9595
sampling-times = <2 3 5 8 20 62 182 602>;
96-
st,adc-sequencer = "FULLY_CONFIGURABLE";
97-
st,adc-oversampler = "OVERSAMPLER_NONE";
96+
st,adc-sequencer = "programmable";
97+
st,adc-oversampler = "none";
9898
st,adc-internal-regulator = "startup-sw-delay";
9999
st,adc-has-differential-support;
100100
status = "disabled";

‎dts/arm/st/f3/stm32f373.dtsi‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -258,8 +258,8 @@
258258
#io-channel-cells = <1>;
259259
resolutions = <STM32F1_ADC_RES(12)>;
260260
sampling-times = <2 8 14 29 42 56 72 240>;
261-
st,adc-sequencer = "FULLY_CONFIGURABLE";
262-
st,adc-oversampler = "OVERSAMPLER_NONE";
261+
st,adc-sequencer = "programmable";
262+
st,adc-oversampler = "none";
263263
st,adc-internal-regulator = "none";
264264
status = "disabled";
265265
};

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