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| 1 | +/* |
| 2 | + * Copyright (c) 2021, Yonatan Schachter |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#ifndef __RP2040_PINCTRL_H__ |
| 8 | +#define __RP2040_PINCTRL_H__ |
| 9 | + |
| 10 | +#define RP2_PINCTRL_GPIO_FUNC_XIP 0 |
| 11 | +#define RP2_PINCTRL_GPIO_FUNC_SPI 1 |
| 12 | +#define RP2_PINCTRL_GPIO_FUNC_UART 2 |
| 13 | +#define RP2_PINCTRL_GPIO_FUNC_I2C 3 |
| 14 | +#define RP2_PINCTRL_GPIO_FUNC_PWM 4 |
| 15 | +#define RP2_PINCTRL_GPIO_FUNC_SIO 5 |
| 16 | +#define RP2_PINCTRL_GPIO_FUNC_PIO0 6 |
| 17 | +#define RP2_PINCTRL_GPIO_FUNC_PIO1 7 |
| 18 | +#define RP2_PINCTRL_GPIO_FUNC_GPCK 8 |
| 19 | +#define RP2_PINCTRL_GPIO_FUNC_USB 9 |
| 20 | +#define RP2_PINCTRL_GPIO_FUNC_NULL 0xf |
| 21 | + |
| 22 | +#define RP2_ALT_FUNC_POS 0 |
| 23 | +#define RP2_ALT_FUNC_MASK 0xf |
| 24 | + |
| 25 | +#define RP2_PIN_NUM_POS 4 |
| 26 | +#define RP2_PIN_NUM_MASK 0x1f |
| 27 | + |
| 28 | +#define RP2040_PINMUX(pin_num, alt_func) (pin_num << RP2_PIN_NUM_POS | \ |
| 29 | + alt_func << RP2_ALT_FUNC_POS) |
| 30 | + |
| 31 | +#define UART0_TX_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_UART) |
| 32 | +#define UART0_RX_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_UART) |
| 33 | +#define UART0_CTS_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_UART) |
| 34 | +#define UART0_RTS_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_UART) |
| 35 | +#define UART1_TX_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_UART) |
| 36 | +#define UART1_RX_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_UART) |
| 37 | +#define UART1_CTS_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_UART) |
| 38 | +#define UART1_RTS_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_UART) |
| 39 | +#define UART1_TX_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_UART) |
| 40 | +#define UART1_RX_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_UART) |
| 41 | +#define UART1_CTS_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_UART) |
| 42 | +#define UART1_RTS_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART) |
| 43 | +#define UART0_TX_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_UART) |
| 44 | +#define UART0_RX_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_UART) |
| 45 | +#define UART0_CTS_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_UART) |
| 46 | +#define UART0_RTS_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_UART) |
| 47 | +#define UART0_TX_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_UART) |
| 48 | +#define UART0_RX_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_UART) |
| 49 | +#define UART0_CTS_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_UART) |
| 50 | +#define UART0_RTS_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_UART) |
| 51 | +#define UART1_TX_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_UART) |
| 52 | +#define UART1_RX_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_UART) |
| 53 | +#define UART1_CTS_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART) |
| 54 | +#define UART1_RTS_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART) |
| 55 | +#define UART1_TX_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_UART) |
| 56 | +#define UART1_RX_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_UART) |
| 57 | +#define UART1_CTS_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART) |
| 58 | +#define UART1_RTS_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_UART) |
| 59 | +#define UART0_TX_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_UART) |
| 60 | +#define UART0_RX_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_UART) |
| 61 | + |
| 62 | +#endif /* __RP2040_PINCTRL_H__ */ |
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