dts: bindings: clock: Change clock control binding for Renesas RA

quytranpzz · thenguyenyf · commit 62de5424e980 · 2024-08-22T13:50:22.000+07:00
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.

Signed-off-by: Quy Tran &lt;quy.tran.pz@renesas.com&gt;
diff --git a/boards/renesas/ek_ra4e2/doc/index.rst b/boards/renesas/ek_ra4e2/doc/index.rst
@@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA4E2 board:
 +-----------+------------+----------------------+
 | UART      | on-chip    | serial               |
 +-----------+------------+----------------------+
+| CLOCK     | on-chip    | clock control        |
++-----------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 
diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts
@@ -56,7 +56,6 @@
 	source = <RA_PLL_SOURCE_MAIN_OSC>;
 	div = <RA_PLL_DIV_1>;
 	mul = <10 0>;
-	freq = <DT_FREQ_M(200)>;
 	status = "okay";
 };
 
diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig
@@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
 
 CONFIG_BUILD_OUTPUT_HEX=y
 CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra4m2/doc/index.rst b/boards/renesas/ek_ra4m2/doc/index.rst
@@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA4M2 board:
 +-----------+------------+----------------------+
 | UART      | on-chip    | serial               |
 +-----------+------------+----------------------+
+| CLOCK     | on-chip    | clock control        |
++-----------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 
diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts
@@ -56,7 +56,6 @@
 	source = <RA_PLL_SOURCE_MAIN_OSC>;
 	div = <RA_PLL_DIV_3>;
 	mul = <25 0>;
-	freq = <DT_FREQ_M(200)>;
 	status = "okay";
 };
 
diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig
@@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
 
 CONFIG_BUILD_OUTPUT_HEX=y
 CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra4m3/doc/index.rst b/boards/renesas/ek_ra4m3/doc/index.rst
@@ -98,6 +98,8 @@ The below features are currently supported on Zephyr OS for EK-RA4M3 board:
 +-----------+------------+----------------------+
 | UART      | on-chip    | serial               |
 +-----------+------------+----------------------+
+| CLOCK     | on-chip    | clock control        |
++-----------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 
diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts
@@ -56,7 +56,6 @@
 	source = <RA_PLL_SOURCE_MAIN_OSC>;
 	div = <RA_PLL_DIV_3>;
 	mul = <25 0>;
-	freq = <DT_FREQ_M(200)>;
 	status = "okay";
 };
 
diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig
@@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
 
 CONFIG_BUILD_OUTPUT_HEX=y
 CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra4w1/doc/index.rst b/boards/renesas/ek_ra4w1/doc/index.rst
@@ -88,6 +88,8 @@ The below features are currently supported on Zephyr OS for EK-RA4W1 board:
 +-----------+------------+----------------------+
 | UART      | on-chip    | serial               |
 +-----------+------------+----------------------+
+| CLOCK     | on-chip    | clock control        |
++-----------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 
diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig
@@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
 
 CONFIG_BUILD_OUTPUT_HEX=y
 CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
@@ -83,7 +83,6 @@
 			source = <RA_PLL_SOURCE_MAIN_OSC>;
 			div = <RA_PLL_DIV_1>;
 			mul = <10 0>;
-			freq = <DT_FREQ_M(200)>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
@@ -133,7 +133,6 @@
 			div = <RA_PLL_DIV_3>;
 			mul = <25 0>;
 			status = "disabled";
-			freq = <DT_FREQ_M(200)>;
 		};
 
 		pll2: pll2 {
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
@@ -143,7 +143,6 @@
 			div = <RA_PLL_DIV_3>;
 			mul = <25 0>;
 			status = "disabled";
-			freq = <DT_FREQ_M(200)>;
 		};
 
 		pll2: pll2 {
diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
@@ -77,7 +77,6 @@
 			source = <RA_PLL_SOURCE_MAIN_OSC>;
 			div = <RA_PLL_DIV_2>;
 			mul = <12 0>;
-			freq = <DT_FREQ_M(48)>;
 			status = "disabled";
 		};
 
diff --git a/soc/renesas/ra/ra4e2/Kconfig b/soc/renesas/ra/ra4e2/Kconfig
@@ -6,6 +6,7 @@ config SOC_SERIES_RA4E2
 	select CPU_HAS_ARM_MPU
 	select CPU_CORTEX_M33
 	select HAS_RENESAS_RA_FSP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select CPU_CORTEX_M_HAS_DWT
 	select ARMV8_M_DSP
 	select CPU_HAS_FPU
diff --git a/soc/renesas/ra/ra4e2/soc.c b/soc/renesas/ra/ra4e2/soc.c
@@ -37,6 +37,7 @@ volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 static int renesas_ra4e2_init(void)
 {
 	extern volatile uint16_t g_protect_counters[];
+
 	for (uint32_t i = 0; i < 4; i++) {
 		g_protect_counters[i] = 0;
 	}
@@ -61,7 +62,6 @@ static int renesas_ra4e2_init(void)
 
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
-	bsp_clock_init();
 
 	return 0;
 }
diff --git a/soc/renesas/ra/ra4e2/soc.h b/soc/renesas/ra/ra4e2/soc.h
@@ -13,4 +13,4 @@
 
 #include <bsp_api.h>
 
-#endif /* ZEPHYR_SOC_RENESAS_RA4_SOC_H_ */
+#endif /* ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_ */
diff --git a/soc/renesas/ra/ra4m2/Kconfig b/soc/renesas/ra/ra4m2/Kconfig
@@ -7,6 +7,7 @@ config SOC_SERIES_RA4M2
 	select CPU_CORTEX_M33
 	select HAS_RENESAS_RA_FSP
 	select CPU_CORTEX_M_HAS_DWT
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select ARMV8_M_DSP
 	select CPU_HAS_FPU
 	select FPU
diff --git a/soc/renesas/ra/ra4m2/soc.c b/soc/renesas/ra/ra4m2/soc.c
@@ -37,6 +37,7 @@ volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 static int renesas_ra4m2_init(void)
 {
 	extern volatile uint16_t g_protect_counters[];
+
 	for (uint32_t i = 0; i < 4; i++) {
 		g_protect_counters[i] = 0;
 	}
@@ -61,7 +62,6 @@ static int renesas_ra4m2_init(void)
 
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
-	bsp_clock_init();
 
 	return 0;
 }
diff --git a/soc/renesas/ra/ra4m3/Kconfig b/soc/renesas/ra/ra4m3/Kconfig
@@ -6,6 +6,7 @@ config SOC_SERIES_RA4M3
 	select CPU_HAS_ARM_MPU
 	select CPU_CORTEX_M33
 	select HAS_RENESAS_RA_FSP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select CPU_CORTEX_M_HAS_DWT
 	select ARMV8_M_DSP
 	select CPU_HAS_FPU
diff --git a/soc/renesas/ra/ra4m3/soc.c b/soc/renesas/ra/ra4m3/soc.c
@@ -37,6 +37,7 @@ volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 static int renesas_ra4m3_init(void)
 {
 	extern volatile uint16_t g_protect_counters[];
+
 	for (uint32_t i = 0; i < 4; i++) {
 		g_protect_counters[i] = 0;
 	}
@@ -61,7 +62,6 @@ static int renesas_ra4m3_init(void)
 
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
-	bsp_clock_init();
 
 	return 0;
 }
diff --git a/soc/renesas/ra/ra4w1/Kconfig b/soc/renesas/ra/ra4w1/Kconfig
@@ -6,6 +6,7 @@ config SOC_SERIES_RA4W1
 	select CPU_HAS_ARM_MPU
 	select CPU_CORTEX_M4
 	select HAS_RENESAS_RA_FSP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
 	select FPU
diff --git a/soc/renesas/ra/ra4w1/soc.c b/soc/renesas/ra/ra4w1/soc.c
@@ -38,7 +38,6 @@ static int renesas_ra4w1_init(void)
 {
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
-	bsp_clock_init();
 
 	return 0;
 }

Original file line number	Diff line number	Diff line change
`@@ -15,3 +15,4 @@ CONFIG_CONSOLE=y`
`15`	`15`
`16`	`16`	`CONFIG_BUILD_OUTPUT_HEX=y`
`17`	`17`	`CONFIG_BUILD_NO_GAP_FILL=y`
	`18`	`+CONFIG_CLOCK_CONTROL=y`