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drivers: mfd: add support for stm32 mfd timers
Added multi functional device driver. Added support for new timer base (mfd stm32 timers), which aims to be more versatile. Signed-off-by: Max van Kessel <[email protected]>
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‎drivers/CMakeLists.txt‎

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@@ -4,6 +4,7 @@ add_definitions(-D__ZEPHYR_SUPERVISOR__)
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add_subdirectory(console)
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add_subdirectory(interrupt_controller)
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add_subdirectory(mfd)
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add_subdirectory_if_kconfig(adc)
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add_subdirectory_if_kconfig(clock_control)

‎drivers/Kconfig‎

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@@ -95,4 +95,6 @@ source "drivers/eeprom/Kconfig"
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source "drivers/peci/Kconfig"
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source "drivers/mfd/Kconfig"
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endmenu

‎drivers/mfd/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources_ifdef(CONFIG_MFD_TIMER_STM32 mfd_timer_stm32.c)

‎drivers/mfd/Kconfig‎

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# MFD configuration options
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# Copyright (c) 2019 Max van Kessel
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# SPDX-License-Identifier: Apache-2.0
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menu "Multifunction Device Drivers"
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config MFD_TIMER_STM32
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bool "STM32 MCU timer driver"
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depends on SOC_FAMILY_STM32
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help
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Enable This option enables the base timer driver for STM32 family of
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processors. Say y if you wish to use timer interface on STM32
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MCU.
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endmenu

‎drivers/mfd/mfd_timer_stm32.c‎

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/*
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* Copyright (c) 2019 Max van Kessel
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <soc.h>
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#include <device.h>
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#include <clock_control/stm32_clock_control.h>
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#include <mfd/mfd_timer_stm32.h>
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#define DEV_CFG(dev) \
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((const struct mfd_timer_stm32_config * const) \
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(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct mfd_timer_stm32_data * const)(dev)->driver_data)
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struct mfd_timer_stm32_config {
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u32_t tim_base; /**< Timer base */
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struct stm32_pclken pclken; /**< subsystem driving this peripheral */
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u8_t align_mode;
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u8_t dir;
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u8_t msm;
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u8_t slave_mode;
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u8_t slave_trig;
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u8_t master_trig;
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u32_t prescaler;
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};
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enum {
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ALIGN_EDGE = 0,
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ALIGN_CENTER_1,
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ALIGN_CENTER_2,
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ALIGN_CENTER_3
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};
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static inline void tim_stm32_get_clock(struct device *dev)
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{
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struct mfd_timer_stm32_data *data = DEV_DATA(dev);
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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data->clock = clk;
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}
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static u32_t tim_stm32_get_rate(u32_t bus_clk,
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clock_control_subsys_t *sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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u32_t tim_clk, apb_psc;
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if (pclken->bus == STM32_CLOCK_BUS_APB1) {
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apb_psc = CONFIG_CLOCK_STM32_APB1_PRESCALER;
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}
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#if !defined(CONFIG_SOC_SERIES_STM32F0X) && !defined(CONFIG_SOC_SERIES_STM32G0X)
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else {
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apb_psc = CONFIG_CLOCK_STM32_APB2_PRESCALER;
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}
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#endif
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/*
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* If the APB prescaler equals 1, the timer clock frequencies
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* are set to the same frequency as that of the APB domain.
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* Otherwise, they are set to twice (×2) the frequency of the
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* APB domain.
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*/
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if (apb_psc == 1U) {
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tim_clk = bus_clk;
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} else {
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tim_clk = bus_clk * 2U;
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}
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return tim_clk;
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}
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static int init(struct device *dev)
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{
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int err = -EIO;
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const struct mfd_timer_stm32_config *cfg = DEV_CFG(dev);
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struct mfd_timer_stm32_data *data = DEV_DATA(dev);
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tim_stm32_get_clock(dev);
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/* enable clock */
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if (clock_control_on(data->clock,
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(clock_control_subsys_t *)&cfg->pclken) == 0) {
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err = 0;
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}
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if (err == 0) {
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TIM_TypeDef *tim = (TIM_TypeDef *)cfg->tim_base;
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u32_t mode = 0;
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data->tim = tim;
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/* TODO: create binding for me */
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LL_TIM_SetClockSource(tim, LL_TIM_CLOCKSOURCE_INTERNAL);
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if (cfg->prescaler > 0) {
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LL_TIM_SetPrescaler(tim, cfg->prescaler - 1);
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} else {
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LL_TIM_SetPrescaler(tim, 0);
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}
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/* TODO find a more consistent solution for all soc's */
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if (cfg->align_mode == ALIGN_EDGE) {
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mode = cfg->dir << TIM_CR1_DIR_Pos;
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} else {
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mode = cfg->align_mode << TIM_CR1_CMS_Pos;
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}
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LL_TIM_SetCounterMode(tim, mode);
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if (cfg->msm > 0) {
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/* Trigger input delayed to allow synchronization */
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LL_TIM_EnableMasterSlaveMode(tim);
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}
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mode = cfg->slave_mode << TIM_SMCR_SMS_Pos;
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LL_TIM_SetSlaveMode(tim, mode);
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if (cfg->slave_mode != 0) {
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mode = cfg->slave_trig << TIM_SMCR_TS_Pos;
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LL_TIM_SetTriggerInput(tim, mode);
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}
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mode = cfg->master_trig << TIM_CR2_MMS_Pos;
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LL_TIM_SetTriggerOutput(tim, mode);
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/* TODO: create binding for me ?*/
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LL_TIM_DisableARRPreload(tim);
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}
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return err;
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}
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static void enable(struct device *dev)
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{
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const struct mfd_timer_stm32_config *cfg = DEV_CFG(dev);
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/* Timer is enabled by master timer if slave mode is set */
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if ((cfg->slave_mode << TIM_SMCR_SMS_Pos) != LL_TIM_SLAVEMODE_TRIGGER) {
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struct mfd_timer_stm32_data *data = DEV_DATA(dev);
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LL_TIM_EnableCounter(data->tim);
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}
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}
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static void disable(struct device *dev)
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{
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struct mfd_timer_stm32_data *data = DEV_DATA(dev);
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LL_TIM_DisableCounter(data->tim);
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}
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static int get_cycles_per_sec(struct device *dev, u64_t *cycles)
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{
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int err = -EINVAL;
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const struct mfd_timer_stm32_config *cfg = DEV_CFG(dev);
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struct mfd_timer_stm32_data *data = DEV_DATA(dev);
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u32_t bus_clk, tim_clk;
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if (cycles != NULL) {
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/* Timer clock depends on APB prescaler */
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err = clock_control_get_rate(data->clock,
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(clock_control_subsys_t *)&cfg->pclken,
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&bus_clk);
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if (err >= 0) {
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tim_clk = tim_stm32_get_rate(bus_clk,
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(clock_control_subsys_t *)&cfg->pclken);
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*cycles = (u64_t) (tim_clk / (cfg->prescaler));
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err = 0;
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}
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}
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return err;
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}
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static const struct mfd_timer_stm32 api = {
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.enable = enable,
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.disable = disable,
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.get_cycles_per_sec = get_cycles_per_sec,
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};
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#define TIMER_DEVICE_INIT(n) \
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static struct mfd_timer_stm32_data mfd_timer_stm32_dev_data_ ## n; \
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static const struct mfd_timer_stm32_config mfd_timer_stm32_dev_cfg_ ## n = { \
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.tim_base = DT_INST_## n ##_ST_STM32_TIMERS_BASE_ADDRESS, \
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.align_mode = DT_INST_## n ##_ST_STM32_TIMERS_ST_ALIGN_MODE_ENUM,\
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.dir = DT_INST_## n ##_ST_STM32_TIMERS_ST_COUNTER_DIR_ENUM, \
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.msm = DT_INST_## n ##_ST_STM32_TIMERS_ST_MASTER_SLAVE_MODE, \
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.slave_mode = DT_INST_## n ##_ST_STM32_TIMERS_ST_SLAVE_MODE, \
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.slave_trig = DT_INST_## n ##_ST_STM32_TIMERS_ST_SLAVE_TRIGGER_IN, \
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.master_trig = DT_INST_## n ##_ST_STM32_TIMERS_ST_MASTER_TRIGGER_OUT,\
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.prescaler = DT_INST_## n ##_ST_STM32_TIMERS_ST_PRESCALER, \
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.pclken = { \
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.bus = DT_INST_## n ##_ST_STM32_TIMERS_CLOCK_BUS, \
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.enr = DT_INST_## n ##_ST_STM32_TIMERS_CLOCK_BITS }, \
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}; \
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\
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DEVICE_AND_API_INIT(timer_stm32_ ## n, \
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DT_INST_## n ##_ST_STM32_TIMERS_LABEL, \
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&init, \
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&mfd_timer_stm32_dev_data_ ## n, \
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&mfd_timer_stm32_dev_cfg_ ## n, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&api)
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#ifdef DT_INST_0_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(0);
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#endif
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#ifdef DT_INST_1_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(1);
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#endif
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#ifdef DT_INST_2_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(2);
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#endif
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#ifdef DT_INST_3_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(3);
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#endif
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#ifdef DT_INST_4_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(4);
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#endif
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#ifdef DT_INST_6_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(6);
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#endif
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#ifdef DT_INST_7_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(7);
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#endif
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#ifdef DT_INST_8_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(8);
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#endif
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#ifdef DT_INST_9_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(9);
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#endif
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#ifdef DT_INST_10_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(10);
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#endif
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#ifdef DT_INST_11_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(11);
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#endif
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#ifdef DT_INST_12_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(12);
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#endif
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#ifdef DT_INST_13_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(13);
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#endif
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#ifdef DT_INST_14_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(14);
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#endif
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#ifdef DT_INST_15_ST_STM32_TIMERS
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TIMER_DEVICE_INIT(15);
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#endif
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‎drivers/mfd/mfd_timer_stm32.h‎

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/*
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* Copyright (c) 2019 Max van Kessel
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_MFD_MFD_TIMER_STM32_H_
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#define ZEPHYR_DRIVERS_MFD_MFD_TIMER_STM32_H_
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#include <errno.h>
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#include <zephyr/types.h>
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#include <device.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief MFD timer data structure
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*/
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struct mfd_timer_stm32_data {
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TIM_TypeDef *tim; /**< Base address */
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struct device *clock; /**< Clock device */
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};
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typedef void (*mfd_timer_stm32_enable_t)(struct device *dev);
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typedef void (*mfd_timer_stm32_disable_t)(struct device *dev);
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typedef int (*mfd_timer_stm32_get_cycles_per_sec_t)(struct device *dev,
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u64_t *cycles);
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struct mfd_timer_stm32 {
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mfd_timer_stm32_enable_t enable;
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mfd_timer_stm32_disable_t disable;
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mfd_timer_stm32_get_cycles_per_sec_t get_cycles_per_sec;
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};
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/**
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* @brief Enable stm32 timer device
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* @param dev The device to enable
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*/
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static inline void mfd_timer_stm32_enable(struct device *dev)
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{
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const struct mfd_timer_stm32 *api = (const struct mfd_timer_stm32 *)
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dev->driver_api;
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return api->enable(dev);
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}
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/**
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* @brief Disable stm32 timer device
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* @param dev The device to disable
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*/
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static inline void mfd_timer_stm32_disable(struct device *dev)
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{
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const struct mfd_timer_stm32 *api = (const struct mfd_timer_stm32 *)
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dev->driver_api;
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return api->disable(dev);
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}
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/**
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* @brief Get the clock rate (cycles per second)
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* @param dev Pointer to timer device structure
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* @param cycles Pointer to the memory to store clock rate
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* (cycles per second)
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* @retval 0 for success
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* @retval negative errno code
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*/
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static inline int mfd_timer_stm32_get_cycles_per_sec(struct device *dev,
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u64_t *cycles)
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{
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const struct mfd_timer_stm32 *api = (const struct mfd_timer_stm32 *)
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dev->driver_api;
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return api->get_cycles_per_sec(dev, cycles);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_MFD_MFD_TIMER_STM32_H_ */

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