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Commit 63eef35

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Josuah Demangeon
committed
use existing datastructures to infer state
To avoid replicated state across the driver to keep in sync, get the information about which state drivers are in. Signed-off-by: Josuah Demangeon <[email protected]>
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drivers/usb/uhc/uhc_dwc2.c

Lines changed: 3 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -120,13 +120,6 @@ enum uhc_dwc2_chan_event {
120120
DWC2_CHAN_EVENT_NONE,
121121
};
122122

123-
enum uhc_dwc2_chan_state {
124-
/* Pipe is active */
125-
UHC_CHAN_STATE_ACTIVE,
126-
/* Pipe is halted */
127-
UHC_CHAN_STATE_HALTED,
128-
};
129-
130123
enum uhc_dwc2_ctrl_stage {
131124
CTRL_STAGE_DATA0 = 0,
132125
CTRL_STAGE_DATA2 = 1,
@@ -137,8 +130,6 @@ enum uhc_dwc2_ctrl_stage {
137130
struct uhc_dwc2_chan {
138131
/* XFER queuing related */
139132
sys_dlist_t xfer_pending_list;
140-
int num_xfer_pending;
141-
int num_xfer_done;
142133
/* Pointer to the transfer associated with the buffer */
143134
struct uhc_transfer *xfer;
144135
/* Interval in frames (FS) or microframes (HS) */
@@ -147,8 +138,6 @@ struct uhc_dwc2_chan {
147138
uint32_t offset;
148139
/* Type of endpoint */
149140
enum uhc_dwc2_xfer_type type;
150-
/* Pipe status/state/events related */
151-
enum uhc_dwc2_chan_state state;
152141
enum uhc_dwc2_chan_event last_event;
153142
/* The index of the channel */
154143
uint8_t chan_idx;
@@ -172,10 +161,7 @@ struct uhc_dwc2_chan {
172161
uint8_t is_hs: 1;
173162
/* Support for Low-Speed is via a Full-Speed HUB */
174163
uint8_t ls_via_fs_hub: 1;
175-
uint8_t waiting_halt: 1;
176164
uint8_t chan_cmd_processing: 1;
177-
/* Is channel enabled */
178-
uint8_t active: 1;
179165
/* Halt has been requested */
180166
uint8_t halt_requested: 1;
181167
/* TODO: Lists of pending and done? */
@@ -416,9 +402,6 @@ static void dwc2_channel_configure(const struct device *dev, struct uhc_dwc2_cha
416402
struct usb_dwc2_reg *const dwc2 = config->base;
417403
const struct usb_dwc2_host_chan *chan_regs = UHC_DWC2_CHAN_REG(dwc2, chan->chan_idx);
418404

419-
__ASSERT(!chan->active && !chan->halt_requested,
420-
"Cannot change endpoint characteristics while channel is active or halted");
421-
422405
uint32_t hcchar =
423406
((uint32_t)chan->ep_mps << USB_DWC2_HCCHAR0_MPS_POS) |
424407
((uint32_t)USB_EP_GET_IDX(chan->ep_addr) << USB_DWC2_HCCHAR0_EPNUM_POS) |
@@ -815,12 +798,6 @@ enum uhc_dwc2_chan_event uhc_dwc2_hal_chan_decode_intr(const struct device *dev,
815798
/* Clear the interrupt bits by writing them back */
816799
sys_write32(hcint, (mem_addr_t)&chan_regs->hcint);
817800

818-
/*
819-
* Note:
820-
* We don't assert on (chan->active) here as it could have been already cleared
821-
* by usb_dwc_hal_chan_request_halt()
822-
*/
823-
824801
/*
825802
* Note:
826803
* Do not change order of checks as some events take precedence over others.
@@ -840,7 +817,6 @@ enum uhc_dwc2_chan_event uhc_dwc2_hal_chan_decode_intr(const struct device *dev,
840817
} else {
841818
chan_event = DWC2_CHAN_EVENT_CPLT;
842819
}
843-
chan->active = 0;
844820
} else if (hcint & USB_DWC2_HCINT_XFERCOMPL) {
845821
/* Note:
846822
* The channel isn't halted yet, so we need to halt it manually to stop the
@@ -933,7 +909,6 @@ static inline void _buffer_fill_ctrl(struct uhc_dwc2_chan *chan, struct uhc_tran
933909
static void IRAM_ATTR _buffer_fill(struct uhc_dwc2_chan *chan)
934910
{
935911
struct uhc_transfer *xfer = chan_get_next_xfer(chan);
936-
chan->num_xfer_pending--;
937912

938913
/* TODO: Double buffering scheme? */
939914

@@ -1043,20 +1018,6 @@ static void IRAM_ATTR _buffer_exec_proceed(const struct device *dev, struct uhc_
10431018
sys_write32(hcchar, (mem_addr_t)&chan_regs->hcchar);
10441019
}
10451020

1046-
static inline bool _buffer_can_fill(struct uhc_dwc2_chan *chan)
1047-
{
1048-
/* TODO: Double buffering scheme? */
1049-
/* We can only fill if there are pending XFRs and at least one unfilled buffer */
1050-
return (chan->num_xfer_pending > 0);
1051-
}
1052-
1053-
static inline bool _buffer_can_exec(struct uhc_dwc2_chan *chan)
1054-
{
1055-
/* TODO: Double buffering scheme? */
1056-
/* For one buffer we can execute it always */
1057-
return true;
1058-
}
1059-
10601021
/*
10611022
* Decode a channel interrupt and take appropriate action.
10621023
* Interrupt context.
@@ -1087,15 +1048,12 @@ static void uhc_dwc2_handle_chan_intr(const struct device *dev, struct uhc_dwc2_
10871048
case DWC2_CHAN_EVENT_HALT_REQ:
10881049
LOG_ERR("Channel halt request handling not implemented yet");
10891050

1090-
__ASSERT(chan->waiting_halt, "Pipe is not watiting to be halted");
1091-
10921051
/* TODO: Implement halting the ongoing transfer */
10931052

10941053
/* Hint:
10951054
* We've halted a transfer, so we need to trigger the chan callback
10961055
* Halt request event is triggered when packet is successful completed.
10971056
* But just treat all halted transfers as errors
1098-
* chan->state = UHC_CHAN_STATE_HALTED;
10991057
* Notify the task waiting for the chan halt or halt it right away
11001058
* _internal_chan_event_notify(chan, true);
11011059
*/
@@ -1462,8 +1420,6 @@ static inline int uhc_dwc2_chan_config(const struct device *dev, uint8_t chan_id
14621420
chan->dev_addr = dev_addr;
14631421
chan->ls_via_fs_hub = 0;
14641422
chan->interval = 0;
1465-
chan->offset = 0;
1466-
chan->state = UHC_CHAN_STATE_ACTIVE;
14671423

14681424
/* TODO: enter critical section */
14691425
if (!priv->conn_dev_ena) {
@@ -1677,16 +1633,14 @@ static inline int uhc_dwc2_submit_ctrl_xfer(const struct device *dev, struct uhc
16771633
}
16781634

16791635
sys_dlist_append(&chan->xfer_pending_list, &xfer->node);
1680-
chan->num_xfer_pending++;
16811636

16821637
key = irq_lock();
16831638

1684-
if (_buffer_can_fill(chan)) {
1639+
if (!sys_dlist_is_empty(&chan->xfer_pending_list)) {
16851640
_buffer_fill(chan);
16861641
}
1687-
if (_buffer_can_exec(chan)) {
1688-
_buffer_exec(dev, chan);
1689-
}
1642+
1643+
_buffer_exec(dev, chan);
16901644

16911645
irq_unlock(key);
16921646

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