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drivers: serial: Add support for Renesas RZ/V2H
Add support for Renesas RZ/V2H Signed-off-by: Tien Nguyen <[email protected]> Signed-off-by: Quang Le <[email protected]>
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6 files changed

+304
-56
lines changed

6 files changed

+304
-56
lines changed

‎drivers/serial/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RX_QEMU uart_renesas_rx_sci_qem
7373
zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZA2M_SCIF uart_renesas_rza2m_scif.c)
7474
zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZ_SCI uart_renesas_rz_sci.c)
7575
zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZ_SCIF uart_renesas_rz_scif.c)
76+
zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZ_SCI_B uart_renesas_rz_sci.c)
7677
zephyr_library_sources_ifdef(CONFIG_UART_RPI_PICO_PIO uart_rpi_pico_pio.c)
7778
zephyr_library_sources_ifdef(CONFIG_UART_RTS5912 uart_realtek_rts5912.c)
7879
zephyr_library_sources_ifdef(CONFIG_UART_RTT_DRIVER uart_rtt.c)

‎drivers/serial/Kconfig.renesas_rz

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,17 @@ config UART_RENESAS_RZ_SCI
2323
help
2424
Enable Renesas RZ SCI UART Driver.
2525

26+
config UART_RENESAS_RZ_SCI_B
27+
bool "Renesas RZ SCI-B UART"
28+
default y
29+
depends on DT_HAS_RENESAS_RZ_SCI_B_UART_ENABLED
30+
select PINCTRL
31+
select SERIAL_HAS_DRIVER
32+
select SERIAL_SUPPORT_INTERRUPT
33+
select USE_RZ_FSP_SCI_UART
34+
help
35+
Enable Renesas RZ SCI-B UART Driver.
36+
2637
if UART_RENESAS_RZ_SCIF
2738

2839
config UART_RENESAS_RZG_INIT_DELAY_MS

‎drivers/serial/uart_renesas_rz_sci.c

Lines changed: 115 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,26 @@
99
#include <zephyr/drivers/pinctrl.h>
1010
#include <zephyr/logging/log.h>
1111
#include <zephyr/irq.h>
12+
#if defined(CONFIG_UART_RENESAS_RZ_SCI_B)
13+
#include "r_sci_b_uart.h"
14+
#else
1215
#include "r_sci_uart.h"
16+
#endif
17+
18+
#if defined(CONFIG_UART_RENESAS_RZ_SCI_B)
19+
#define R_SCI0_Type R_SCI_B0_Type
20+
#define SCI_UART_CLOCK_INT SCI_B_UART_CLOCK_INT
21+
#define SCI_UART_RS485_DISABLE SCI_B_UART_RS485_DISABLE
22+
#define SCI_UART_FLOW_CONTROL_RTS SCI_B_UART_FLOW_CONTROL_RTS
23+
#define SCI_UART_RX_FIFO_TRIGGER_MAX SCI_B_UART_RX_FIFO_TRIGGER_MAX
24+
#define SCI_UART_START_BIT_FALLING_EDGE SCI_B_UART_START_BIT_FALLING_EDGE
25+
#define SCI_UART_RS485_DE_POLARITY_HIGH SCI_B_UART_RS485_DE_POLARITY_HIGH
26+
#define SCI_UART_NOISE_CANCELLATION_ENABLE SCI_B_UART_NOISE_CANCELLATION_ENABLE
27+
#define SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS
28+
typedef sci_b_baud_setting_t sci_baud_setting_t;
29+
typedef sci_b_uart_extended_cfg_t sci_uart_extended_cfg_t;
30+
typedef sci_b_uart_instance_ctrl_t sci_uart_instance_ctrl_t;
31+
#endif
1332

1433
LOG_MODULE_REGISTER(rz_sci_uart);
1534

@@ -41,11 +60,26 @@ struct uart_rz_sci_data {
4160
#define SCI_UART_ERROR_RATE_x1000 (5000)
4261

4362
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
63+
#if defined(CONFIG_UART_RENESAS_RZ_SCI_B)
64+
void sci_b_uart_rxi_isr(void);
65+
void sci_b_uart_txi_isr(void);
66+
void sci_b_uart_tei_isr(void);
67+
void sci_b_uart_eri_isr(void);
68+
#define SCI_RXI_ISR sci_b_uart_rxi_isr
69+
#define SCI_TXI_ISR sci_b_uart_txi_isr
70+
#define SCI_TEI_ISR sci_b_uart_tei_isr
71+
#define SCI_ERI_ISR sci_b_uart_eri_isr
72+
#else
4473
void sci_uart_rxi_isr(void);
4574
void sci_uart_txi_isr(void);
4675
void sci_uart_tei_isr(void);
4776
void sci_uart_eri_isr(void);
48-
#endif
77+
#define SCI_RXI_ISR sci_uart_rxi_isr
78+
#define SCI_TXI_ISR sci_uart_txi_isr
79+
#define SCI_TEI_ISR sci_uart_tei_isr
80+
#define SCI_ERI_ISR sci_uart_eri_isr
81+
#endif /* CONFIG_UART_RENESAS_RZ_SCI_B */
82+
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
4983

5084
static int uart_rz_sci_poll_in(const struct device *dev, unsigned char *c)
5185
{
@@ -111,6 +145,14 @@ static int uart_rz_sci_apply_config(const struct device *dev)
111145
sci_uart_extended_cfg_t *fsp_config_extend = (sci_uart_extended_cfg_t *)fsp_cfg->p_extend;
112146

113147
fsp_err_t fsp_err;
148+
#if defined(CONFIG_UART_RENESAS_RZ_SCI_B)
149+
uint32_t baud_rate = uart_config->baudrate;
150+
bool enable_bitrate_modulation = false;
151+
uint32_t error_rate_x_1000 = SCI_UART_ERROR_RATE_x1000;
152+
153+
fsp_err = R_SCI_B_UART_BaudCalculate(baud_rate, enable_bitrate_modulation,
154+
error_rate_x_1000, &baud_setting);
155+
#else
114156
sci_uart_baud_calculation_t baud_target;
115157

116158
baud_target.baudrate = uart_config->baudrate;
@@ -119,6 +161,7 @@ static int uart_rz_sci_apply_config(const struct device *dev)
119161

120162
fsp_err = R_SCI_UART_BaudCalculate(&baud_target, fsp_config_extend->clock_source,
121163
&baud_setting);
164+
#endif /* CONFIG_UART_RENESAS_RZ_SCI_B */
122165
if (fsp_err) {
123166
return -EIO;
124167
}
@@ -229,7 +272,7 @@ static int uart_rz_sci_fifo_fill(const struct device *dev, const uint8_t *tx_dat
229272
fsp_ctrl->tx_src_bytes = size;
230273
fsp_ctrl->p_tx_src = tx_data;
231274

232-
sci_uart_txi_isr();
275+
SCI_TXI_ISR();
233276

234277
return (size - fsp_ctrl->tx_src_bytes);
235278
}
@@ -242,7 +285,7 @@ static int uart_rz_sci_fifo_read(const struct device *dev, uint8_t *rx_data, con
242285
fsp_ctrl->rx_dest_bytes = size;
243286
fsp_ctrl->p_rx_dest = rx_data;
244287

245-
sci_uart_rxi_isr();
288+
SCI_RXI_ISR();
246289

247290
data->int_data.rx_fifo_busy = false;
248291

@@ -320,52 +363,6 @@ static int uart_rz_sci_irq_update(const struct device *dev)
320363
ARG_UNUSED(dev);
321364
return 1;
322365
}
323-
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
324-
325-
static DEVICE_API(uart, uart_rz_sci_driver_api) = {
326-
.poll_in = uart_rz_sci_poll_in,
327-
.poll_out = uart_rz_sci_poll_out,
328-
.err_check = uart_rz_sci_err_check,
329-
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
330-
.configure = uart_rz_sci_configure,
331-
.config_get = uart_rz_sci_config_get,
332-
#endif
333-
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
334-
.fifo_fill = uart_rz_sci_fifo_fill,
335-
.fifo_read = uart_rz_sci_fifo_read,
336-
.irq_rx_enable = uart_rz_sci_irq_rx_enable,
337-
.irq_rx_disable = uart_rz_sci_irq_rx_disable,
338-
.irq_tx_enable = uart_rz_sci_irq_tx_enable,
339-
.irq_tx_disable = uart_rz_sci_irq_tx_disable,
340-
.irq_tx_ready = uart_rz_sci_irq_tx_ready,
341-
.irq_rx_ready = uart_rz_sci_irq_rx_ready,
342-
.irq_is_pending = uart_rz_sci_irq_is_pending,
343-
.irq_callback_set = uart_rz_sci_irq_callback_set,
344-
.irq_update = uart_rz_sci_irq_update,
345-
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
346-
};
347-
348-
static int uart_rz_init(const struct device *dev)
349-
{
350-
const struct uart_rz_sci_config *config = dev->config;
351-
struct uart_rz_sci_data *data = dev->data;
352-
int ret;
353-
354-
ret = pinctrl_apply_state(config->pin_config, PINCTRL_STATE_DEFAULT);
355-
if (ret < 0) {
356-
return ret;
357-
}
358-
359-
/* uart_rz_sci_apply_config must be called first before open api */
360-
ret = uart_rz_sci_apply_config(dev);
361-
if (ret < 0) {
362-
return ret;
363-
}
364-
365-
config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
366-
367-
return 0;
368-
}
369366

370367
static void uart_rz_sci_rxi_isr(const struct device *dev)
371368
{
@@ -388,12 +385,12 @@ static void uart_rz_sci_txi_isr(const struct device *dev)
388385

389386
static void uart_rz_sci_tei_isr(const struct device *dev)
390387
{
391-
sci_uart_tei_isr();
388+
SCI_TEI_ISR();
392389
}
393390

394391
static void uart_rz_sci_eri_isr(const struct device *dev)
395392
{
396-
sci_uart_eri_isr();
393+
SCI_ERI_ISR();
397394
}
398395

399396
static void uart_rz_sci_event_handler(uart_callback_args_t *p_args)
@@ -411,18 +408,73 @@ static void uart_rz_sci_event_handler(uart_callback_args_t *p_args)
411408
case UART_EVENT_TX_DATA_EMPTY:
412409
break;
413410
case UART_EVENT_TX_COMPLETE:
411+
data->fsp_ctrl->p_reg->CCR0_b.TE = 1;
414412
break;
415413
default:
416414
break;
417415
}
418416
}
419417

418+
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
419+
420+
static DEVICE_API(uart, uart_rz_sci_driver_api) = {
421+
.poll_in = uart_rz_sci_poll_in,
422+
.poll_out = uart_rz_sci_poll_out,
423+
.err_check = uart_rz_sci_err_check,
424+
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
425+
.configure = uart_rz_sci_configure,
426+
.config_get = uart_rz_sci_config_get,
427+
#endif
428+
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
429+
.fifo_fill = uart_rz_sci_fifo_fill,
430+
.fifo_read = uart_rz_sci_fifo_read,
431+
.irq_rx_enable = uart_rz_sci_irq_rx_enable,
432+
.irq_rx_disable = uart_rz_sci_irq_rx_disable,
433+
.irq_tx_enable = uart_rz_sci_irq_tx_enable,
434+
.irq_tx_disable = uart_rz_sci_irq_tx_disable,
435+
.irq_tx_ready = uart_rz_sci_irq_tx_ready,
436+
.irq_rx_ready = uart_rz_sci_irq_rx_ready,
437+
.irq_is_pending = uart_rz_sci_irq_is_pending,
438+
.irq_callback_set = uart_rz_sci_irq_callback_set,
439+
.irq_update = uart_rz_sci_irq_update,
440+
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
441+
};
442+
443+
static int uart_rz_init(const struct device *dev)
444+
{
445+
const struct uart_rz_sci_config *config = dev->config;
446+
struct uart_rz_sci_data *data = dev->data;
447+
int ret;
448+
449+
ret = pinctrl_apply_state(config->pin_config, PINCTRL_STATE_DEFAULT);
450+
if (ret < 0) {
451+
return ret;
452+
}
453+
454+
/* uart_rz_sci_apply_config must be called first before open api */
455+
ret = uart_rz_sci_apply_config(dev);
456+
if (ret < 0) {
457+
return ret;
458+
}
459+
460+
config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
461+
462+
return 0;
463+
}
464+
420465
#define SCI_NODE(idx) DT_INST_PARENT(idx)
466+
467+
#ifdef CONFIG_CPU_CORTEX_M
468+
#define GET_IRQ_FLAGS(index, irq_name) 0
469+
#else /* Cortex-A/R */
470+
#define GET_IRQ_FLAGS(index, irq_name) DT_IRQ_BY_NAME(index, irq_name, flags)
471+
#endif
472+
421473
#define UART_RZ_IRQ_CONNECT(n, irq_name, isr) \
422474
do { \
423475
IRQ_CONNECT(DT_IRQ_BY_NAME(SCI_NODE(n), irq_name, irq), \
424476
DT_IRQ_BY_NAME(SCI_NODE(n), irq_name, priority), isr, \
425-
DEVICE_DT_INST_GET(n), DT_IRQ_BY_NAME(SCI_NODE(n), irq_name, flags)); \
477+
DEVICE_DT_INST_GET(n), GET_IRQ_FLAGS(SCI_NODE(n), irq_name)); \
426478
irq_enable(DT_IRQ_BY_NAME(SCI_NODE(n), irq_name, irq)); \
427479
} while (0)
428480

@@ -440,7 +492,6 @@ static void uart_rz_sci_event_handler(uart_callback_args_t *p_args)
440492
.noise_cancel = SCI_UART_NOISE_CANCELLATION_ENABLE, \
441493
.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, \
442494
.p_baud_setting = &g_uart##n##_baud_setting, \
443-
.clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK, \
444495
.flow_control = SCI_UART_FLOW_CONTROL_RTS, \
445496
.flow_control_pin = 0xFF, \
446497
.rs485_setting = \
@@ -450,7 +501,9 @@ static void uart_rz_sci_event_handler(uart_callback_args_t *p_args)
450501
.assertion_time = 1, \
451502
.negation_time = 1, \
452503
}, \
453-
}; \
504+
COND_CODE_1(CONFIG_UART_RENESAS_RZ_SCI_B, \
505+
(.half_data_setting = {.enable = 0}), \
506+
(.clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK)) }; \
454507
static uart_cfg_t g_uart##n##_cfg = { \
455508
.channel = DT_PROP(SCI_NODE(n), channel), \
456509
.p_extend = &g_uart##n##_cfg_extend, \
@@ -470,8 +523,9 @@ static void uart_rz_sci_event_handler(uart_callback_args_t *p_args)
470523
PINCTRL_DT_DEFINE(SCI_NODE(n)); \
471524
static struct uart_rz_sci_config uart_rz_config_##n = { \
472525
.pin_config = PINCTRL_DT_DEV_CONFIG_GET(SCI_NODE(n)), \
473-
.fsp_api = &g_uart_on_sci, \
474-
}; \
526+
COND_CODE_1(CONFIG_UART_RENESAS_RZ_SCI_B, \
527+
(.fsp_api = &g_uart_on_sci_b), \
528+
(.fsp_api = &g_uart_on_sci)) }; \
475529
static sci_uart_instance_ctrl_t g_uart##n##_ctrl; \
476530
static struct uart_rz_sci_data uart_rz_sci_data_##n = { \
477531
.fsp_ctrl = &g_uart##n##_ctrl, \
@@ -499,3 +553,8 @@ static void uart_rz_sci_event_handler(uart_callback_args_t *p_args)
499553
&uart_rz_sci_driver_api);
500554

501555
DT_INST_FOREACH_STATUS_OKAY(UART_RZ_INIT)
556+
557+
#undef DT_DRV_COMPAT
558+
#define DT_DRV_COMPAT renesas_rz_sci_b_uart
559+
560+
DT_INST_FOREACH_STATUS_OKAY(UART_RZ_INIT)

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