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drivers: added clock control driver for MSPM0
added clock_control support for TI MSPM0 Family Signed-off-by: Jackson Farley <[email protected]>
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‎drivers/clock_control/CMakeLists.txt‎

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@@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SCG_K4 clock_cont
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SIM clock_control_mcux_sim.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_SYSCON clock_control_mcux_syscon.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCM clock_control_npcm.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MSPM0 clock_control_mspm0.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NPCX clock_control_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_control_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c)

‎drivers/clock_control/Kconfig‎

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@@ -52,6 +52,8 @@ source "drivers/clock_control/Kconfig.mcux_syscon"
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source "drivers/clock_control/Kconfig.npcm"
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source "drivers/clock_control/Kconfig.mspm0"
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source "drivers/clock_control/Kconfig.npcx"
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source "drivers/clock_control/Kconfig.rv32m1"

‎drivers/clock_control/Kconfig.mspm0‎

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# TI MSPM0 Family
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# Copyright (c) 2024, Texas Instruments Inc.
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_MSPM0
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bool "TI MSPM0 clock"
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default y
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depends on SOC_FAMILY_TI_MSPM0
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help
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This option enables the TI MSPM0 Clock Control Enabler
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config CLOCK_CONTROL_MSPM0_USE_PLL
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bool "TI MSPM0 Use PLL"
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default n
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help
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This option enables the PLL on MSPM0 devices (if equipped)

‎drivers/clock_control/clock_control_mspm0.c‎

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/*
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* Copyright (c) 2024 Texas Instruments
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/mspm0_clock_control.h>
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#include <ti/driverlib/driverlib.h>
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#define ULPCLK_DIV CONCAT(DL_SYSCTL_ULPCLK_DIV_, DT_PROP(DT_NODELABEL(clkmux), uclk_div))
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay)
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#define MSPM0_PLL_ENABLED 1
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#endif
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static const DL_SYSCTL_SYSPLLConfig clock_mspm0_cfg_syspll;
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static int clock_mspm0_on(const struct device *dev, clock_control_subsys_t sys)
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{
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return 0;
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}
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static int clock_mspm0_off(const struct device *dev, clock_control_subsys_t sys)
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{
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return 0;
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}
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static enum clock_control_status clock_mspm0_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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return CLOCK_CONTROL_STATUS_UNKNOWN;
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}
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static int clock_mspm0_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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struct mspm0_clockSys *clockSys = (struct mspm0_clockSys *)sys;
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uint8_t rateNotFound = 0;
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switch (clockSys->bus) {
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case MSPM0_CLOCK_BUS_LFCLK:
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*rate = 32768;
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break;
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case MSPM0_CLOCK_BUS_ULPCLK:
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*rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC /
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DT_PROP(DT_NODELABEL(clkmux), uclk_div);
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break;
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case MSPM0_CLOCK_BUS_MCLK:
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*rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
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break;
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case MSPM0_CLOCK_BUS_MFPCLK:
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*rate = 4000000;
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break;
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case MSPM0_CLOCK_BUS_MFCLK:
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case MSPM0_CLOCK_BUS_CANCLK:
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default:
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rateNotFound = 1;
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break;
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}
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if (rateNotFound == 1) {
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return -ENOTSUP;
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} else {
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return 0;
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}
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}
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static int clock_mspm0_set_rate(const struct device *dev, clock_control_subsys_t sys,
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clock_control_subsys_rate_t rate)
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{
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return -ENOTSUP;
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}
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static int clock_mspm0_configure(const struct device *dev, clock_control_subsys_t sys, void *data)
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{
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return -ENOTSUP;
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}
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static int clock_mspm0_init(const struct device *dev)
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{
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/* setup clocks based on specific rates */
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DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
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DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *)&clock_mspm0_cfg_syspll);
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DL_SYSCTL_setULPCLKDivider(ULPCLK_DIV);
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DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL);
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return 0;
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}
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static const struct clock_control_driver_api clock_mspm0_driver_api = {
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.on = clock_mspm0_on,
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.off = clock_mspm0_off,
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.get_status = clock_mspm0_get_status,
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.get_rate = clock_mspm0_get_rate,
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.set_rate = clock_mspm0_set_rate,
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.configure = clock_mspm0_configure};
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DEVICE_DT_DEFINE(DT_NODELABEL(clkmux), &clock_mspm0_init, NULL, NULL, NULL, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_mspm0_driver_api);
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#if MSPM0_PLL_ENABLED
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/* basic checks of the devicetree to follow */
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#if (DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div) && \
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DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk0_div))
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#error "Only CLK2X or CLK0 can be enabled at a time on the PLL"
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#endif
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#define GENERATE_PLL_STRUCT() \
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static const DL_SYSCTL_SYSPLLConfig clock_mspm0_cfg_syspll = { \
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.inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_32_48_MHZ, \
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.rDivClk2x = (DT_PROP_OR(DT_NODELABEL(pll), clk2x_div, 1) - 1), \
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.rDivClk1 = (DT_PROP_OR(DT_NODELABEL(pll), clk1_div, 1) - 1), \
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.rDivClk0 = (DT_PROP_OR(DT_NODELABEL(pll), clk0_div, 1) - 1), \
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.qDiv = (DT_PROP(DT_NODELABEL(pll), q_div) - 1), \
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.pDiv = CONCAT(DL_SYSCTL_SYSPLL_PDIV_, DT_PROP(DT_NODELABEL(pll), p_div)), \
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.sysPLLMCLK = COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div), \
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(DL_SYSCTL_SYSPLL_MCLK_CLK2X), (DL_SYSCTL_SYSPLL_MCLK_CLK0)), \
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.enableCLK2x = COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk2x_div), \
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(DL_SYSCTL_SYSPLL_CLK2X_ENABLE), (DL_SYSCTL_SYSPLL_CLK2X_DISABLE)), \
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.enableCLK1 = COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk1_div), \
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(DL_SYSCTL_SYSPLL_CLK1_ENABLE), (DL_SYSCTL_SYSPLL_CLK1_DISABLE)), \
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.enableCLK0 = COND_CODE_1(DT_NODE_HAS_PROP(DT_NODELABEL(pll), clk0_div), \
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(DL_SYSCTL_SYSPLL_CLK0_ENABLE), (DL_SYSCTL_SYSPLL_CLK0_DISABLE)), \
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.sysPLLRef = COND_CODE_1(DT_CLOCKS_CELL(DT_NODELABEL(pll), clocks), \
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(DL_SYSCTL_SYSPLL_REF_HFCLK), (DL_SYSCTL_SYSPLL_REF_SYSOSC)), \
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};
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GENERATE_PLL_STRUCT()
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#endif /* MSPM0_PLL_ENABLED */

‎include/zephyr/drivers/clock_control/mspm0_clock_control.h‎

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/*
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* Copyright (c) 2024 Texas Instruments Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MSPM0_CLOCK_CONTROL
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#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MSPM0_CLOCK_CONTROL
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#include <zephyr/dt-bindings/clock/mspm0_clock.h>
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struct mspm0_clockSys {
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uint32_t bus;
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};
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#define MSPM0_CLOCK_SUBSYS_FN(index) {.bus = DT_INST_CLOCKS_CELL(index, bus)}
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#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_MSPM0_CLOCK_CONTROL */

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