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| 1 | +/* |
| 2 | + * Copyright (c) 2022 Zephyr authors |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#ifndef H_OS_MGMT_PROCESSOR_ |
| 8 | +#define H_OS_MGMT_PROCESSOR_ |
| 9 | + |
| 10 | +#ifdef __cplusplus |
| 11 | +extern "C" { |
| 12 | +#endif |
| 13 | + |
| 14 | +/** |
| 15 | + * Processor name (used in uname output command) |
| 16 | + * Will be unknown if processor type is not listed |
| 17 | + * (List extracted from /cmake/gcc-m-cpu.cmake) |
| 18 | + */ |
| 19 | +#if defined(CONFIG_ARM) |
| 20 | +#if defined(CONFIG_CPU_CORTEX_M0) |
| 21 | +#define PROCESSOR_NAME "cortex-m0" |
| 22 | +#elif defined(CONFIG_CPU_CORTEX_M0PLUS) |
| 23 | +#define PROCESSOR_NAME "cortex-m0plus" |
| 24 | +#elif defined(CONFIG_CPU_CORTEX_M1) |
| 25 | +#define PROCESSOR_NAME "cortex-m1" |
| 26 | +#elif defined(CONFIG_CPU_CORTEX_M3) |
| 27 | +#define PROCESSOR_NAME "cortex-m3" |
| 28 | +#elif defined(CONFIG_CPU_CORTEX_M4) |
| 29 | +#define PROCESSOR_NAME "cortex-m4" |
| 30 | +#elif defined(CONFIG_CPU_CORTEX_M7) |
| 31 | +#define PROCESSOR_NAME "cortex-m7" |
| 32 | +#elif defined(CONFIG_CPU_CORTEX_M23) |
| 33 | +#define PROCESSOR_NAME "cortex-m23" |
| 34 | +#elif defined(CONFIG_CPU_CORTEX_M33) |
| 35 | +#if defined(CONFIG_ARMV8_M_DSP) |
| 36 | +#define PROCESSOR_NAME "cortex-m33" |
| 37 | +#else |
| 38 | +#define PROCESSOR_NAME "cortex-m33+nodsp" |
| 39 | +#endif |
| 40 | +#elif defined(CONFIG_CPU_CORTEX_M55) |
| 41 | +#if defined(CONFIG_ARMV8_1_M_MVEF) |
| 42 | +#define PROCESSOR_NAME "cortex-m55" |
| 43 | +#elif defined(CONFIG_ARMV8_1_M_MVEI) |
| 44 | +#define PROCESSOR_NAME "cortex-m55+nomve.fp" |
| 45 | +#elif defined(CONFIG_ARMV8_M_DSP) |
| 46 | +#define PROCESSOR_NAME "cortex-m55+nomve" |
| 47 | +#else |
| 48 | +#define PROCESSOR_NAME "cortex-m55+nodsp" |
| 49 | +#endif |
| 50 | +#elif defined(CONFIG_CPU_CORTEX_R4) |
| 51 | +#if defined(CONFIG_FPU) && defined(CONFIG_CPU_HAS_VFP) |
| 52 | +#define PROCESSOR_NAME "cortex-r4f" |
| 53 | +#else |
| 54 | +#define PROCESSOR_NAME "cortex-r4" |
| 55 | +#endif |
| 56 | +#elif defined(CONFIG_CPU_CORTEX_R5) |
| 57 | +#if defined(CONFIG_FPU) && defined(CONFIG_CPU_HAS_VFP) |
| 58 | +#if !defined(CONFIG_VFP_FEATURE_DOUBLE_PRECISION) |
| 59 | +#define PROCESSOR_NAME "cortex-r5+nofp.dp" |
| 60 | +#else |
| 61 | +#define PROCESSOR_NAME "cortex-r5" |
| 62 | +#endif |
| 63 | +#else |
| 64 | +#define PROCESSOR_NAME "cortex-r5+nofp" |
| 65 | +#endif |
| 66 | +#elif defined(CONFIG_CPU_CORTEX_R7) |
| 67 | +#if defined(CONFIG_FPU) && defined(CONFIG_CPU_HAS_VFP) |
| 68 | +#if !defined(CONFIG_VFP_FEATURE_DOUBLE_PRECISION) |
| 69 | +#define PROCESSOR_NAME "cortex-r7+nofp.dp" |
| 70 | +#else |
| 71 | +#define PROCESSOR_NAME "cortex-r7" |
| 72 | +#endif |
| 73 | +#else |
| 74 | +#define PROCESSOR_NAME "cortex-r7+nofp" |
| 75 | +#endif |
| 76 | +#elif defined(CONFIG_CPU_CORTEX_R52) |
| 77 | +#if defined(CONFIG_FPU) && defined(CONFIG_CPU_HAS_VFP) |
| 78 | +#if !defined(CONFIG_VFP_FEATURE_DOUBLE_PRECISION) |
| 79 | +#define PROCESSOR_NAME "cortex-r52+nofp.dp" |
| 80 | +#else |
| 81 | +#define PROCESSOR_NAME "cortex-r52" |
| 82 | +#endif |
| 83 | +#else |
| 84 | +#define PROCESSOR_NAME "cortex-r52" |
| 85 | +#endif |
| 86 | +#elif defined(CONFIG_CPU_CORTEX_A9) |
| 87 | +#define PROCESSOR_NAME "cortex-a9" |
| 88 | +#endif |
| 89 | +#elif defined(CONFIG_ARM64) |
| 90 | +#if defined(CONFIG_CPU_CORTEX_A53) |
| 91 | +#define PROCESSOR_NAME "cortex-a53" |
| 92 | +#if defined(CONFIG_CPU_CORTEX_A55) |
| 93 | +#define PROCESSOR_NAME "cortex-a55" |
| 94 | +#elif defined(CONFIG_CPU_CORTEX_A72) |
| 95 | +#define PROCESSOR_NAME "cortex-a72" |
| 96 | +#elif defined(CONFIG_CPU_CORTEX_R82) |
| 97 | +#define PROCESSOR_NAME "armv8.4-a+nolse" |
| 98 | +#endif |
| 99 | +#endif |
| 100 | +#elif defined(CONFIG_ARC) |
| 101 | +#if defined(CONFIG_CPU_EM4_FPUS) |
| 102 | +#define PROCESSOR_NAME "em4_fpus" |
| 103 | +#elif defined(CONFIG_CPU_EM4_DMIPS) |
| 104 | +#define PROCESSOR_NAME "em4_dmips" |
| 105 | +#elif defined(CONFIG_CPU_EM4_FPUDA) |
| 106 | +#define PROCESSOR_NAME "em4_fpuda" |
| 107 | +#elif defined(CONFIG_CPU_HS3X) |
| 108 | +#define PROCESSOR_NAME "archs" |
| 109 | +#elif defined(CONFIG_CPU_HS5X) |
| 110 | +#define PROCESSOR_NAME "hs5x" |
| 111 | +#elif defined(CONFIG_CPU_HS6X) |
| 112 | +#define PROCESSOR_NAME "hs6x" |
| 113 | +#elif defined(CONFIG_CPU_EM4) |
| 114 | +#define PROCESSOR_NAME "arcem" |
| 115 | +#elif defined(CONFIG_CPU_EM6) |
| 116 | +#define PROCESSOR_NAME "arcem" |
| 117 | +#endif |
| 118 | +#elif defined(CONFIG_X86) |
| 119 | +#if defined(CONFIG_X86_64) |
| 120 | +#define PROCESSOR_NAME "x86_64" |
| 121 | +#else |
| 122 | +#define PROCESSOR_NAME "x86" |
| 123 | +#endif |
| 124 | +#elif defined(CONFIG_RISCV) |
| 125 | +#define PROCESSOR_NAME "riscv" |
| 126 | +#endif |
| 127 | + |
| 128 | +#ifndef PROCESSOR_NAME |
| 129 | +#warning "Processor type could not be determined" |
| 130 | +#define PROCESSOR_NAME "unknown" |
| 131 | +#endif |
| 132 | + |
| 133 | +#ifdef __cplusplus |
| 134 | +} |
| 135 | +#endif |
| 136 | + |
| 137 | +#endif /* H_OS_MGMT_PROCESSOR_ */ |
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