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soc: ene: kb106x soc
Add ENE KB106X SoC Signed-off-by: Steven Chang <[email protected]>
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‎soc/ene/kb106x/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(common)
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add_subdirectory(${SOC_SERIES})

‎soc/ene/kb106x/Kconfig

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# Copyright (c) 2025 ENE Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_KB106X
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select BUILD_OUTPUT_HEX
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select BUILD_OUTPUT_BIN
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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if SOC_FAMILY_KB106X
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rsource "*/Kconfig"
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endif # SOC_FAMILY_KB106X

‎soc/ene/kb106x/Kconfig.defconfig

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# Copyright (c) 2025 ENE Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_KB106X
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rsource "*/Kconfig.defconfig"
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endif # SOC_FAMILY_KB106X

‎soc/ene/kb106x/Kconfig.soc

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# Copyright (c) 2025 ENE Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_KB106X
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bool
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config SOC_FAMILY
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default "kb106x" if SOC_FAMILY_KB106X
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rsource "*/Kconfig.soc"

‎soc/ene/kb106x/common/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_include_directories(.)
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zephyr_library_sources_ifdef(CONFIG_PM power.c)

‎soc/ene/kb106x/common/power.c

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/*
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* Copyright (c) 2025 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/pm/pm.h>
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#include <power.h>
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void kb106x_soc_deep_sleep(void)
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{
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#if defined(CONFIG_TRACING)
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sys_trace_idle();
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#endif
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/*
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* PRIMASK is always cleared on ARMv7-M and ARMv8-M (not used
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* for interrupt locking), and configuring BASEPRI to the lowest
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* priority to ensure wake-up will cause interrupts to be serviced
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* before entering low power state.
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*
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* Set PRIMASK before configuring BASEPRI to prevent interruption
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* before wake-up.
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*/
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__disable_irq();
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SCB->SCR |= BIT(2);
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/*
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* Set wake-up interrupt priority to the lowest and synchronize to
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* ensure that this is visible to the WFI instruction.
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*/
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__set_BASEPRI(0);
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__ISB();
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__DSB();
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__WFI();
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SCB->SCR &= ~BIT(2);
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#if defined(CONFIG_TRACING)
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sys_trace_idle_exit();
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#endif
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__enable_irq();
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__ISB();
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}
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void kb106x_soc_idle(void)
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{
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#if defined(CONFIG_TRACING)
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sys_trace_idle();
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#endif
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/*
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* PRIMASK is always cleared on ARMv7-M and ARMv8-M (not used
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* for interrupt locking), and configuring BASEPRI to the lowest
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* priority to ensure wake-up will cause interrupts to be serviced
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* before entering low power state.
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*
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* Set PRIMASK before configuring BASEPRI to prevent interruption
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* before wake-up.
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*/
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__disable_irq();
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SCB->SCR &= ~BIT(2);
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/*
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* Set wake-up interrupt priority to the lowest and synchronize to
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* ensure that this is visible to the WFI instruction.
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*/
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__set_BASEPRI(0);
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__ISB();
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__DSB();
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__WFI();
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#if defined(CONFIG_TRACING)
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sys_trace_idle_exit();
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#endif
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__enable_irq();
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__ISB();
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}
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__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(substate_id);
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switch (state) {
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case PM_STATE_ACTIVE:
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break;
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case PM_STATE_RUNTIME_IDLE:
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__fallthrough;
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case PM_STATE_SUSPEND_TO_IDLE:
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kb106x_soc_idle();
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break;
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case PM_STATE_STANDBY:
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__fallthrough;
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case PM_STATE_SUSPEND_TO_RAM:
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__fallthrough;
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case PM_STATE_SUSPEND_TO_DISK:
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__fallthrough;
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case PM_STATE_SOFT_OFF:
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kb106x_soc_deep_sleep();
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break;
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default:
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k_cpu_idle();
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break;
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}
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}
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__weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(state);
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ARG_UNUSED(substate_id);
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}

‎soc/ene/kb106x/common/power.h

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/*
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* Copyright (c) 2025 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _KB106X_POWER_H_
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#define _KB106X_POWER_H_
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void kb106x_soc_deep_sleep(void);
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void kb106x_soc_idle(void);
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#endif /* _KB106X_POWER_H_ */

‎soc/ene/kb106x/common/reg/gcfg.h

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/*
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* Copyright (c) 2025 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ENE_KB106X_GCFG_H
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#define ENE_KB106X_GCFG_H
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/**
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* Structure type to access General Configuration (GCFG).
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*/
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struct gcfg_regs {
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volatile uint8_t IDV; /*Version ID Register */
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volatile uint8_t Reserved0; /*Reserved */
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volatile uint16_t IDC; /*Chip ID Register */
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volatile uint32_t FWID; /*Firmware ID Register */
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volatile uint32_t MCURST; /*MCU Reset Control Register */
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volatile uint32_t RSTFLAG; /*Reset Pending Flag Register */
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volatile uint32_t GPIOALT; /*GPIO Alternate Register */
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volatile uint8_t GPIOBPC1513; /*GPIO Bypass Control Register */
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volatile uint8_t GPIOBPC1718; /*GPIO Bypass Control Register */
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volatile uint8_t GPIOBPC7E6B; /*GPIO Bypass Control Register */
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volatile uint8_t Reserved1; /*Reserved */
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volatile uint16_t GPIOMUX; /*GPIO MUX Control Register */
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volatile uint16_t Reserved2; /*Reserved */
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volatile uint8_t I2CSPMS; /*I2CS Pin Map Selection Register */
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volatile uint8_t Reserved3[3]; /*Reserved */
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volatile uint8_t CLKCFG; /*Clock Configuration Register */
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volatile uint8_t Reserved4[3]; /*Reserved */
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volatile uint32_t DPLLFREQ; /*DPLL Frequency Register */
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volatile uint8_t GPIORPSC_C; /*Auto-Reset at Power Sequence Fail Register */
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volatile uint8_t GPIORPSC_5X; /*Auto-Reset at Power Sequence Fail Register */
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volatile uint8_t GPIORPSC_6X; /*Auto-Reset at Power Sequence Fail Register */
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volatile uint8_t Reserved5; /*Reserved */
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volatile uint32_t GCFGMISC; /*Misc. Register */
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volatile uint8_t EXTIE; /*Extended Command Interrupt Enable Register */
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volatile uint8_t Reserved6[3]; /*Reserved */
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volatile uint8_t EXTPF; /*Extended Command Pending Flag Register */
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volatile uint8_t Reserved7[3]; /*Reserved */
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volatile uint32_t EXTARG; /*Extended Command Argument0/1/2 Register */
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volatile uint8_t EXTCMD; /*Extended Command Port Register */
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volatile uint8_t Reserved8[3]; /*Reserved */
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volatile uint32_t ADCOTR; /*ADCO Register */
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volatile uint32_t Reserved9; /*Reserved */
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volatile uint32_t IDSR; /*IDSR Register */
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volatile uint32_t Reserved10[13]; /*Reserved */
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volatile uint32_t TRAPMODE;
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volatile uint32_t CLK1UCFG;
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volatile uint32_t LDO15TRIM;
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};
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#define GCFG_CLKCFG_48M 0x00000014
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#define GCFG_CLKCFG_24M 0x00000004
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/*-- Constant Define -------------------------------------------*/
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#define LDO15_OFFSET 0x22
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#define ECMISC2_OFFSET 0x25
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#define CLOCK_SOURCE_OSC32K 1
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#define CLOCK_SOURCE_EXTERNAL 0
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#define EXTERNAL_CLOCK_GPIO_NUM 0x5D
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#define FREQ_96M48M 0
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#define FREQ_48M24M 1
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#define FREQ_24M12M 2
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#define FREQ_12M06M 3
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#define DPLL_32K_TARGET_VALUE 0x05B9UL
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#define DPLL_SOF_TARGET_VALUE 0xBB80UL
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#define DPLL_DONT_CARE_VALUE 3
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#define DPLL_DISABLE 0
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#define DPLL_SOURCE_SOF 1
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#define DPLL_SOURCE_OSC32K 2
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#define DPLL_SOURCE_EXTCLK 3
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/* gcfg->FWID status flag */
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#define ECFV_NORMAL_RUN 0x00
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#define ECFV_PREPARE_UPDATE_ESCD 0x01
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#define ECFV_UPDATE_ESCD 0x81
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#define ECFV_PREPARE_UPDATE_BIOS 0x02
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#define ECFV_UPDATE_BIOS 0x82
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#define ECFV_PREPARE_ENTER_DEEP_SLEEP 0x03
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#define ECFV_ENTER_DEEP_SLEEP 0x83
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#define S0I3_ENTER_STOP 0x04
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#define NON_DEEP_SLEEP_STATE 0x05
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#define MAIN_LOOP_ENTER_IDLE 0x06
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/* VCC Status */
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#define VCC_0V 0x00
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#define VCC_3P3V 0x01
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#define VCC_1P8V 0x02
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#endif /* ENE_KB106X_GCFG_H */

‎soc/ene/kb106x/common/reg/pmu.h

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/*
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* Copyright (c) 2025 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ENE_KB106X_PMU_H
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#define ENE_KB106X_PMU_H
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/**
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* Structure type to access Power Management Unit (PMU).
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*/
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struct pmu_regs {
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volatile uint8_t PMUIDLE; /*IDLE wakeup by Interrupt Register */
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volatile uint8_t Reserved0[3]; /*Reserved */
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volatile uint32_t PMUSTOP; /*STOP Wakeup Source Register */
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volatile uint8_t PMUSTOPC; /*STOP Control Register */
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volatile uint8_t Reserved1[3]; /*Reserved */
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volatile uint8_t PMUCTRL; /*Control Register */
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volatile uint8_t Reserved2[3]; /*Reserved */
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};
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/* STOP Wakeup Source */
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#define PMU_STOP_WU_GPTD 0x00000001
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#define PMU_STOP_WU_VC0 0x00000002
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#define PMU_STOP_WU_VC1 0x00000004
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#define PMU_STOP_WU_IKB 0x00000010
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#define PMU_STOP_WU_WDT 0x00000100
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#define PMU_STOP_WU_HIBTMR 0x00000400
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#define PMU_STOP_WU_eSPI 0x00010000
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#define PMU_STOP_WU_I2CD32 0x00020000
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#define PMU_STOP_WU_EDI32 0x00040000
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#define PMU_STOP_WU_SWD 0x00080000
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#define PMU_STOP_WU_I2CS0 0x01000000
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#define PMU_STOP_WU_I2CS1 0x02000000
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#define PMU_STOP_WU_USB 0x04000000
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#define PMU_IDLE_WU_ENABLE 0x00000001
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#endif /* ENE_KB106X_PMU_H */

‎soc/ene/kb106x/common/reg/vcc0.h

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/*
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* Copyright (c) 2025 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ENE_KB106X_VCC0_H
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#define ENE_KB106X_VCC0_H
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/**
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* brief Structure type to access VCC0 Power Domain Module (VCC0).
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*/
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struct vcc0_regs {
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volatile uint16_t PAREGPLC; /*VCC0 PLC Register */
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volatile uint16_t PAREGFLAG; /*VCC0 Flag Register */
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volatile uint8_t PB8SCR; /*Power Button Override Control Register */
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volatile uint8_t Reserved0[3]; /*Reserved */
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volatile uint32_t PASCR; /*VCC0 Scratch Register */
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volatile uint32_t Reserved1[5]; /*Reserved */
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volatile uint8_t Reserved2; /*Reserved */
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volatile uint8_t IOSCCFG_T; /*OSC32K Configuration Register */
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volatile uint16_t Reserved3; /*Reserved */
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volatile uint32_t Reserved4[7]; /*Reserved */
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volatile uint8_t HIBTMRCFG; /*Hibernation Timer Configuration Register */
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volatile uint8_t Reserved5[3]; /*Reserved */
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volatile uint8_t HIBTMRIE; /*Hibernation Timer Interrupt Enable Register */
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volatile uint8_t Reserved6[3]; /*Reserved */
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volatile uint8_t HIBTMRPF; /*Hibernation Timer Pending Flag Register */
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volatile uint8_t Reserved7[3]; /*Reserved */
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volatile uint32_t HIBTMRMAT; /*Hibernation Timer Match Value Register */
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volatile uint32_t HIBTMRCNT; /*Hibernation Timer count Value Register */
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};
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#endif /* ENE_KB106X_VCC0_H */

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