drivers: clock_control: Configure STM clock

1.Add "mux-1-dc-0-div" and "mux-2-dc-0-div" property
 in mc_cgm device tree for STM clock divider setting
 and set these properties in frdm_mcxe31b.dts
2.Enable STM peripheral clock in mc_cgm_clock_control_on
 function
3.Support to get STM frequency from mc_cgm_get_subsys_rate
 function
4.Configure STM clock in mc_cgm_init function

Signed-off-by: Felix Wang <[email protected]>

Author: FelixWang47831

boards/nxp/frdm_mcxe31b/frdm_mcxe31b.dts

@@ -164,6 +164,8 @@
 	mux-0-dc-4-div = <4>;
 	mux-0-dc-5-div = <4>;
 	mux-0-dc-6-div = <1>;
+	mux-1-dc-0-div = <1>;
+	mux-2-dc-0-div = <1>;
 };
 
 &stm_0 {

drivers/clock_control/clock_control_nxp_mc_cgm.c

@@ -160,6 +160,19 @@ static int mc_cgm_clock_control_on(const struct device *dev, clock_control_subsy
 	}
 #endif /* defined(CONFIG_I2C_MCUX_LPI2C) */
 
+#if defined(CONFIG_COUNTER_MCUX_STM)
+	switch ((uint32_t)sub_system) {
+	case MCUX_STM0_CLK:
+		CLOCK_EnableClock(kCLOCK_Stm0);
+		break;
+	case MCUX_STM1_CLK:
+		CLOCK_EnableClock(kCLOCK_Stm1);
+		break;
+	default:
+		break;
+	}
+#endif /* defined(CONFIG_COUNTER_MCUX_STM) */
+
 	return 0;
 }
 
@@ -237,6 +250,15 @@ static int mc_cgm_get_subsys_rate(const struct device *dev, clock_control_subsys
 		*rate = CLOCK_GetFlexcanPeClkFreq(5);
 		break;
 #endif /* defined(CONFIG_CAN_MCUX_FLEXCAN) */
+
+#if defined(CONFIG_COUNTER_MCUX_STM)
+	case MCUX_STM0_CLK:
+		*rate = CLOCK_GetStmClkFreq(0);
+		break;
+	case MCUX_STM1_CLK:
+		*rate = CLOCK_GetStmClkFreq(1);
+		break;
+#endif /* defined(CONFIG_COUNTER_MCUX_STM) */
 	}
 	return 0;
 }
@@ -297,6 +319,14 @@ static int mc_cgm_init(const struct device *dev)
 #endif
 	CLOCK_CommonTriggerClkMux0DivUpdate();
 	CLOCK_ProgressiveClockFrequencySwitch(kPLL_PHI0_CLK_to_MUX0, &pcfs_config);
+#if defined(CONFIG_COUNTER_MCUX_STM)
+	CLOCK_SetClkDiv(kCLOCK_DivStm0Clk, NXP_PLL_MUX_1_DC_0_DIV);
+	CLOCK_AttachClk(kAIPS_PLAT_CLK_to_STM0);
+#if defined(FSL_FEATURE_SOC_STM_COUNT) && (FSL_FEATURE_SOC_STM_COUNT == 2U)
+	CLOCK_SetClkDiv(kCLOCK_DivStm1Clk, NXP_PLL_MUX_2_DC_0_DIV);
+	CLOCK_AttachClk(kAIPS_PLAT_CLK_to_STM1);
+#endif /* FSL_FEATURE_SOC_STM_COUNT == 2U */
+#endif /* defined(CONFIG_COUNTER_MCUX_STM) */
 #endif
 
 	/* Set SystemCoreClock variable. */

dts/bindings/clock/nxp,mc-cgm.yaml

@@ -57,6 +57,14 @@ properties:
     type: int
     description: MUX_0_DC_6 divider setting
 
+  mux-1-dc-0-div:
+    type: int
+    description: MUX_1_DC_0 divider setting
+
+  mux-2-dc-0-div:
+    type: int
+    description: MUX_2_DC_0 divider setting
+
   "#clock-cells":
     type: int
     const: 1

include/zephyr/dt-bindings/clock/nxp_mc_cgm.h

@@ -18,6 +18,8 @@
 #define NXP_PLL_MUX_0_DC_4_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_4_div)
 #define NXP_PLL_MUX_0_DC_5_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_5_div)
 #define NXP_PLL_MUX_0_DC_6_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_0_dc_6_div)
+#define NXP_PLL_MUX_1_DC_0_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_1_dc_0_div)
+#define NXP_PLL_MUX_2_DC_0_DIV DT_PROP(DT_NODELABEL(mc_cgm), mux_2_dc_0_div)
 
 /* Note- clock identifiers in this file must be unique,
  * as the driver uses them in a switch case