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ZhaoxiangJinaescolar
ZhaoxiangJin
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aescolar
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drivers: clock_control: imx_ccm_rev2.h: Unified indentation format
Unified indentation format of imx_ccm_rev2.h file. Signed-off-by: Zhaoxiang Jin <[email protected]>
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‎include/zephyr/dt-bindings/clock/imx_ccm_rev2.h

Lines changed: 66 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -13,94 +13,96 @@
1313
* Instance:
1414
* range: 0 - 0xFF, starting from 0
1515
*/
16-
#define IMX_CCM_PERIPHERAL_MASK 0xFF00UL
17-
#define IMX_CCM_INSTANCE_MASK 0xFFUL
16+
#define IMX_CCM_PERIPHERAL_MASK 0xFF00UL
17+
#define IMX_CCM_INSTANCE_MASK 0xFFUL
18+
19+
#define IMX_CCM_CORESYS_CLK 0
20+
#define IMX_CCM_PLATFORM_CLK 0x1UL
21+
#define IMX_CCM_BUS_CLK 0x2UL
1822

19-
#define IMX_CCM_CORESYS_CLK 0
20-
#define IMX_CCM_PLATFORM_CLK 0x1UL
21-
#define IMX_CCM_BUS_CLK 0x2UL
2223
/* LPUART */
23-
#define IMX_CCM_LPUART_CLK 0x300UL
24-
#define IMX_CCM_LPUART1_CLK 0x300UL
25-
#define IMX_CCM_LPUART2_CLK 0x301UL
26-
#define IMX_CCM_LPUART3_CLK 0x302UL
27-
#define IMX_CCM_LPUART4_CLK 0x303UL
28-
#define IMX_CCM_LPUART5_CLK 0x304UL
29-
#define IMX_CCM_LPUART6_CLK 0x305UL
30-
#define IMX_CCM_LPUART7_CLK 0x306UL
31-
#define IMX_CCM_LPUART8_CLK 0x307UL
32-
#define IMX_CCM_LPUART9_CLK 0x308UL
33-
#define IMX_CCM_LPUART10_CLK 0x309UL
34-
#define IMX_CCM_LPUART11_CLK 0x30aUL
35-
#define IMX_CCM_LPUART12_CLK 0x30bUL
24+
#define IMX_CCM_LPUART_CLK 0x300UL
25+
#define IMX_CCM_LPUART1_CLK 0x300UL
26+
#define IMX_CCM_LPUART2_CLK 0x301UL
27+
#define IMX_CCM_LPUART3_CLK 0x302UL
28+
#define IMX_CCM_LPUART4_CLK 0x303UL
29+
#define IMX_CCM_LPUART5_CLK 0x304UL
30+
#define IMX_CCM_LPUART6_CLK 0x305UL
31+
#define IMX_CCM_LPUART7_CLK 0x306UL
32+
#define IMX_CCM_LPUART8_CLK 0x307UL
33+
#define IMX_CCM_LPUART9_CLK 0x308UL
34+
#define IMX_CCM_LPUART10_CLK 0x309UL
35+
#define IMX_CCM_LPUART11_CLK 0x30aUL
36+
#define IMX_CCM_LPUART12_CLK 0x30bUL
3637

3738
/* LPI2C */
38-
#define IMX_CCM_LPI2C_CLK 0x400UL
39-
#define IMX_CCM_LPI2C1_CLK 0x400UL
40-
#define IMX_CCM_LPI2C2_CLK 0x401UL
41-
#define IMX_CCM_LPI2C3_CLK 0x402UL
42-
#define IMX_CCM_LPI2C4_CLK 0x403UL
43-
#define IMX_CCM_LPI2C5_CLK 0x404UL
44-
#define IMX_CCM_LPI2C6_CLK 0x405UL
45-
#define IMX_CCM_LPI2C7_CLK 0x406UL
46-
#define IMX_CCM_LPI2C8_CLK 0x407UL
39+
#define IMX_CCM_LPI2C_CLK 0x400UL
40+
#define IMX_CCM_LPI2C1_CLK 0x400UL
41+
#define IMX_CCM_LPI2C2_CLK 0x401UL
42+
#define IMX_CCM_LPI2C3_CLK 0x402UL
43+
#define IMX_CCM_LPI2C4_CLK 0x403UL
44+
#define IMX_CCM_LPI2C5_CLK 0x404UL
45+
#define IMX_CCM_LPI2C6_CLK 0x405UL
46+
#define IMX_CCM_LPI2C7_CLK 0x406UL
47+
#define IMX_CCM_LPI2C8_CLK 0x407UL
4748

4849
/* LPSPI */
49-
#define IMX_CCM_LPSPI_CLK 0x500UL
50-
#define IMX_CCM_LPSPI1_CLK 0x500UL
51-
#define IMX_CCM_LPSPI2_CLK 0x501UL
52-
#define IMX_CCM_LPSPI3_CLK 0x502UL
53-
#define IMX_CCM_LPSPI4_CLK 0x503UL
54-
#define IMX_CCM_LPSPI5_CLK 0x504UL
55-
#define IMX_CCM_LPSPI6_CLK 0x505UL
56-
#define IMX_CCM_LPSPI7_CLK 0x506UL
57-
#define IMX_CCM_LPSPI8_CLK 0x507UL
50+
#define IMX_CCM_LPSPI_CLK 0x500UL
51+
#define IMX_CCM_LPSPI1_CLK 0x500UL
52+
#define IMX_CCM_LPSPI2_CLK 0x501UL
53+
#define IMX_CCM_LPSPI3_CLK 0x502UL
54+
#define IMX_CCM_LPSPI4_CLK 0x503UL
55+
#define IMX_CCM_LPSPI5_CLK 0x504UL
56+
#define IMX_CCM_LPSPI6_CLK 0x505UL
57+
#define IMX_CCM_LPSPI7_CLK 0x506UL
58+
#define IMX_CCM_LPSPI8_CLK 0x507UL
5859

5960
/* USDHC */
60-
#define IMX_CCM_USDHC1_CLK 0x600UL
61-
#define IMX_CCM_USDHC2_CLK 0x601UL
61+
#define IMX_CCM_USDHC1_CLK 0x600UL
62+
#define IMX_CCM_USDHC2_CLK 0x601UL
6263

6364
/* DMA */
64-
#define IMX_CCM_EDMA_CLK 0x700UL
65-
#define IMX_CCM_EDMA_LPSR_CLK 0x701UL
65+
#define IMX_CCM_EDMA_CLK 0x700UL
66+
#define IMX_CCM_EDMA_LPSR_CLK 0x701UL
6667

6768
/* PWM */
68-
#define IMX_CCM_PWM_CLK 0x800UL
69+
#define IMX_CCM_PWM_CLK 0x800UL
6970

7071
/* CAN */
71-
#define IMX_CCM_CAN_CLK 0x900UL
72-
#define IMX_CCM_CAN1_CLK 0x900UL
73-
#define IMX_CCM_CAN2_CLK 0x901UL
74-
#define IMX_CCM_CAN3_CLK 0x902UL
72+
#define IMX_CCM_CAN_CLK 0x900UL
73+
#define IMX_CCM_CAN1_CLK 0x900UL
74+
#define IMX_CCM_CAN2_CLK 0x901UL
75+
#define IMX_CCM_CAN3_CLK 0x902UL
7576

7677
/* GPT */
77-
#define IMX_CCM_GPT_CLK 0x1000UL
78-
#define IMX_CCM_GPT1_CLK 0x1000UL
79-
#define IMX_CCM_GPT2_CLK 0x1001UL
80-
#define IMX_CCM_GPT3_CLK 0x1002UL
81-
#define IMX_CCM_GPT4_CLK 0x1003UL
82-
#define IMX_CCM_GPT5_CLK 0x1004UL
83-
#define IMX_CCM_GPT6_CLK 0x1005UL
78+
#define IMX_CCM_GPT_CLK 0x1000UL
79+
#define IMX_CCM_GPT1_CLK 0x1000UL
80+
#define IMX_CCM_GPT2_CLK 0x1001UL
81+
#define IMX_CCM_GPT3_CLK 0x1002UL
82+
#define IMX_CCM_GPT4_CLK 0x1003UL
83+
#define IMX_CCM_GPT5_CLK 0x1004UL
84+
#define IMX_CCM_GPT6_CLK 0x1005UL
8485

8586
/* SAI */
86-
#define IMX_CCM_SAI1_CLK 0x2000UL
87-
#define IMX_CCM_SAI2_CLK 0x2001UL
88-
#define IMX_CCM_SAI3_CLK 0x2002UL
89-
#define IMX_CCM_SAI4_CLK 0x2003UL
87+
#define IMX_CCM_SAI1_CLK 0x2000UL
88+
#define IMX_CCM_SAI2_CLK 0x2001UL
89+
#define IMX_CCM_SAI3_CLK 0x2002UL
90+
#define IMX_CCM_SAI4_CLK 0x2003UL
9091

9192
/* ENET */
92-
#define IMX_CCM_ENET_CLK 0x3000UL
93-
#define IMX_CCM_ENET_PLL 0x3001UL
93+
#define IMX_CCM_ENET_CLK 0x3000UL
94+
#define IMX_CCM_ENET_PLL 0x3001UL
9495

9596
/* FLEXSPI */
96-
#define IMX_CCM_FLEXSPI_CLK 0x4000UL
97-
#define IMX_CCM_FLEXSPI2_CLK 0x4001UL
97+
#define IMX_CCM_FLEXSPI_CLK 0x4000UL
98+
#define IMX_CCM_FLEXSPI2_CLK 0x4001UL
99+
98100
/* PIT */
99-
#define IMX_CCM_PIT_CLK 0x5000UL
100-
#define IMX_CCM_PIT1_CLK 0x5001UL
101+
#define IMX_CCM_PIT_CLK 0x5000UL
102+
#define IMX_CCM_PIT1_CLK 0x5001UL
101103

102104
/* ADC */
103-
#define IMX_CCM_LPADC1_CLK 0x6000UL
104-
#define IMX_CCM_LPADC2_CLK 0x6001UL
105+
#define IMX_CCM_LPADC1_CLK 0x6000UL
106+
#define IMX_CCM_LPADC2_CLK 0x6001UL
105107

106108
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */

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