drivers: clock_control: Make LSE driving configurable

benediktibk · benediktibk · commit 66e112ddce39 · 2022-04-21T14:23:23.000+02:00
Make the LSE driving capability configurable for the STM32 series. Fixes #44737. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
diff --git a/drivers/bluetooth/hci/ipm_stm32wb.c b/drivers/bluetooth/hci/ipm_stm32wb.c
@@ -397,6 +397,8 @@ static void start_ble_rf(void)
 	}
 
 #if STM32_LSE_ENABLED
+	/* Configure driving capability */
+	LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
 	/* Select LSE clock */
 	LL_RCC_LSE_Enable();
 	while (!LL_RCC_LSE_IsReady()) {
diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -473,6 +473,9 @@ static void set_up_fixed_clock_sources(void)
 		/* Enable backup domain */
 		LL_PWR_EnableBkUpAccess();
 
+		/* Configure driving capability */
+		LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
+
 		/* Enable LSE oscillator */
 		LL_RCC_LSE_Enable();
 		while (LL_RCC_LSE_IsReady() != 1) {
diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c
@@ -336,6 +336,9 @@ static void set_up_fixed_clock_sources(void)
 			}
 		}
 
+		/* Configure driving capability */
+		LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
+
 		/* Enable LSE Oscillator */
 		LL_RCC_LSE_Enable();
 		/* Wait for LSE ready */
diff --git a/drivers/clock_control/clock_stm32g4.c b/drivers/clock_control/clock_stm32g4.c
@@ -75,6 +75,8 @@ void config_enable_default_clocks(void)
 		/* Wait for Backup domain access */
 	}
 
+	/* Configure driving capability */
+	LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
 	/* Enable LSE Oscillator (32.768 kHz) */
 	LL_RCC_LSE_Enable();
 	while (!LL_RCC_LSE_IsReady()) {
diff --git a/drivers/clock_control/clock_stm32l4_l5_wb_wl.c b/drivers/clock_control/clock_stm32l4_l5_wb_wl.c
@@ -88,6 +88,8 @@ void config_enable_default_clocks(void)
 		/* Wait for Backup domain access */
 	}
 
+	/* Configure driving capability */
+	LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
 	/* Enable LSE Oscillator (32.768 kHz) */
 	LL_RCC_LSE_Enable();
 	while (!LL_RCC_LSE_IsReady()) {
diff --git a/drivers/timer/stm32_lptim_timer.c b/drivers/timer/stm32_lptim_timer.c
@@ -279,6 +279,7 @@ static int sys_clock_driver_init(const struct device *dev)
 
 	/* enable LSE clock */
 	LL_RCC_LSE_DisableBypass();
+	LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
 	LL_RCC_LSE_Enable();
 	while (!LL_RCC_LSE_IsReady()) {
 		/* Wait for LSE ready */
diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi
@@ -49,8 +49,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi
@@ -50,8 +50,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi
@@ -55,8 +55,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi
@@ -52,8 +52,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi
@@ -51,8 +51,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi
@@ -66,8 +66,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi
@@ -56,8 +56,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi
@@ -58,8 +58,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi
@@ -66,8 +66,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi
@@ -64,8 +64,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi
@@ -71,8 +71,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/wl/stm32wl.dtsi b/dts/arm/st/wl/stm32wl.dtsi
@@ -59,8 +59,9 @@
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
+			compatible = "st,stm32-lse-clock";
 			clock-frequency = <32768>;
+			driving-capability = <0>;
 			status = "disabled";
 		};
 
diff --git a/dts/bindings/clock/st,stm32-lse-clock.yaml b/dts/bindings/clock/st,stm32-lse-clock.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2022, SILA Embedded Solutions GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 LSE Clock
+
+compatible: "st,stm32-lse-clock"
+
+include: [fixed-clock.yaml]
+
+properties:
+    driving-capability:
+      type: int
+      required: true
+      description: |
+        LSE driving capability, within the range 0 to 3.
+        0 represents the lowests driving capability, 3
+        the highest.
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h
@@ -180,9 +180,15 @@
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
 #define STM32_LSE_ENABLED	1
 #define STM32_LSE_FREQ		DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
+#define STM32_LSE_DRIVING	0
+#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
+#define STM32_LSE_ENABLED	1
+#define STM32_LSE_FREQ		DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
+#define STM32_LSE_DRIVING	DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
 #else
 #define STM32_LSE_ENABLED	0
 #define STM32_LSE_FREQ		0
+#define STM32_LSE_DRIVING	0
 #endif
 
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \

Original file line number	Diff line number	Diff line change
`@@ -397,6 +397,8 @@ static void start_ble_rf(void)`
`397`	`397`	`}`
`398`	`398`
`399`	`399`	`#if STM32_LSE_ENABLED`
	`400`	`+ /* Configure driving capability */`
	`401`	`+ LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);`
`400`	`402`	`/* Select LSE clock */`
`401`	`403`	`LL_RCC_LSE_Enable();`
`402`	`404`	`while (!LL_RCC_LSE_IsReady()) {`
Original file line number	Diff line number	Diff line change
`@@ -336,6 +336,9 @@ static void set_up_fixed_clock_sources(void)`
`336`	`336`	`}`
`337`	`337`	`}`
`338`	`338`
	`339`	`+ /* Configure driving capability */`
	`340`	`+ LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);`
	`341`	`+`
`339`	`342`	`/* Enable LSE Oscillator */`
`340`	`343`	`LL_RCC_LSE_Enable();`
`341`	`344`	`/* Wait for LSE ready */`
Original file line number	Diff line number	Diff line change
`@@ -75,6 +75,8 @@ void config_enable_default_clocks(void)`
`75`	`75`	`/* Wait for Backup domain access */`
`76`	`76`	`}`
`77`	`77`
	`78`	`+ /* Configure driving capability */`
	`79`	`+ LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);`
`78`	`80`	`/* Enable LSE Oscillator (32.768 kHz) */`
`79`	`81`	`LL_RCC_LSE_Enable();`
`80`	`82`	`while (!LL_RCC_LSE_IsReady()) {`
Original file line number	Diff line number	Diff line change
`@@ -88,6 +88,8 @@ void config_enable_default_clocks(void)`
`88`	`88`	`/* Wait for Backup domain access */`
`89`	`89`	`}`
`90`	`90`
	`91`	`+ /* Configure driving capability */`
	`92`	`+ LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);`
`91`	`93`	`/* Enable LSE Oscillator (32.768 kHz) */`
`92`	`94`	`LL_RCC_LSE_Enable();`
`93`	`95`	`while (!LL_RCC_LSE_IsReady()) {`