board: frdm_mcxn236: Enable MICFIL on frdm_mcxn236

1. Enable MICFIL on frdm_mcxn236 board.
2. MICFIL CLOCK and DATA Pins are conflict with
flexcomm0_lpuart pins, so change flexcomm0_lpuart
pins to 'FC0_P2_PIO0_6' and 'FC0_P3_PIO0_7'.

Signed-off-by: Zhaoxiang Jin <[email protected]>

Author: ZhaoxiangJin

boards/nxp/frdm_mcxn236/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024  NXP
+ * Copyright 2024-2025 NXP
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/init.h>
@@ -103,20 +103,23 @@ void board_early_init_hook(void)
 
 	CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || \
+	DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || \
+	DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil))
 	/* < Set up PLL1 */
 	const pll_setup_t pll1_Setup = {
 		.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
 				 SCG_SPLLCTRL_SELP(1U),
 		.pllndiv = SCG_SPLLNDIV_NDIV(25U),
 		.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
 		.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
-		.pllRate = 24576000U};
+		.pllRate = 24576000U
+	};
 
 	/* Configure PLL1 to the desired values */
 	CLOCK_SetPLL1Freq(&pll1_Setup);
-	/* Set PLL1 CLK0 divider to value 1 */
-	CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
+	/* Set PLL1 CLK0 divider to value 2, then the clock is 12288000Hz. */
+	CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 2U);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm0))
@@ -160,6 +163,7 @@ void board_early_init_hook(void)
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
 	CLOCK_EnableClock(kCLOCK_Gpio0);
+	CLOCK_EnableClock(kCLOCK_Port0);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
@@ -339,6 +343,15 @@ void board_early_init_hook(void)
 	CLOCK_EnableClock(kCLOCK_Sai1);
 #endif
 
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(micfil), okay)
+	CLOCK_SetClkDiv(kCLOCK_DivMicfilFClk, 1U);
+	CLOCK_AttachClk(kPLL1_CLK0_to_MICFILF);
+	CLOCK_EnableClock(kCLOCK_Micfil);
+
+	PORT0->PCR[16] = 0x00001900;
+	PORT0->PCR[17] = 0x00001900;
+#endif
+
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
 }

boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi

@@ -8,8 +8,8 @@
 &pinctrl {
 	pinmux_flexcomm0_lpuart: pinmux_flexcomm0_lpuart {
 		group0 {
-			pinmux = <FC0_P0_PIO0_16>,
-				 <FC0_P1_PIO0_17>;
+			pinmux = <FC0_P2_PIO0_6>,
+				 <FC0_P3_PIO0_7>;
 			slew-rate = "fast";
 			drive-strength = "low";
 			input-enable;
@@ -246,4 +246,14 @@
 			drive-open-drain;
 		};
 	};
+
+	pinmux_micfil: pinmux_micfil {
+		group0 {
+			pinmux = <PDM0_CLK_PIO0_16>,
+				 <PDM0_DATA0_PIO0_17>;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
 };

boards/nxp/frdm_mcxn236/frdm_mcxn236.dts

@@ -441,3 +441,9 @@ dvp_20pin_interface: &video_sdma {};
 	pinctrl-0 = <&pinmux_sai1>;
 	pinctrl-names = "default";
 };
+
+&micfil {
+	status = "okay";
+	pinctrl-0 = <&pinmux_micfil>;
+	pinctrl-names = "default";
+};

dts/arm/nxp/nxp_mcxn23x_common.dtsi

@@ -985,6 +985,48 @@
 		nxp,rx-dma-channel = <3>;
 		status = "disabled";
 	};
+
+	micfil: micfil@10c000 {
+		compatible = "nxp,micfil";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <48 0>;
+		reg = <0x10c000 0x1000>;
+		clocks = <&syscon MCUX_MICFIL_CLK>;
+		status = "disabled";
+		quality-mode = <1>;
+		cic-decimation-rate = <0>;
+		fifo-watermark = <15>;
+		sample-rate = <16000>;
+
+		channel0: micfil-channel@0 {
+			reg = <0>;
+			status = "disabled";
+			dc-remover-cutoff-freq = <2>;
+			decimation-filter-gain = <4>;
+		};
+
+		channel1: micfil-channel@1 {
+			reg = <1>;
+			status = "disabled";
+			dc-remover-cutoff-freq = <2>;
+			decimation-filter-gain = <4>;
+		};
+
+		channel2: micfil-channel@2 {
+			reg = <2>;
+			status = "disabled";
+			dc-remover-cutoff-freq = <2>;
+			decimation-filter-gain = <4>;
+		};
+
+		channel3: micfil-channel@3 {
+			reg = <3>;
+			status = "disabled";
+			dc-remover-cutoff-freq = <2>;
+			decimation-filter-gain = <4>;
+		};
+	};
 };
 
 &systick {