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riscv: Introduce support for RV32E
Introduce support for RV32E. Signed-off-by: Carlo Caione <[email protected]>
1 parent 737dcce commit 673f41e

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8 files changed

+72
-10
lines changed

8 files changed

+72
-10
lines changed

‎arch/riscv/core/coredump.c‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,12 +22,14 @@ struct riscv_arch_block {
2222
uint32_t a3;
2323
uint32_t a4;
2424
uint32_t a5;
25+
#if !defined(CONFIG_RISCV_ISA_RV32E)
2526
uint32_t a6;
2627
uint32_t a7;
2728
uint32_t t3;
2829
uint32_t t4;
2930
uint32_t t5;
3031
uint32_t t6;
32+
#endif /* !CONFIG_RISCV_ISA_RV32E */
3133
uint32_t pc;
3234
} r;
3335
} __packed;
@@ -62,18 +64,20 @@ void arch_coredump_info_dump(const z_arch_esf_t *esf)
6264
arch_blk.r.t0 = esf->t0;
6365
arch_blk.r.t1 = esf->t1;
6466
arch_blk.r.t2 = esf->t2;
65-
arch_blk.r.t3 = esf->t3;
66-
arch_blk.r.t4 = esf->t4;
67-
arch_blk.r.t5 = esf->t5;
68-
arch_blk.r.t6 = esf->t6;
6967
arch_blk.r.a0 = esf->a0;
7068
arch_blk.r.a1 = esf->a1;
7169
arch_blk.r.a2 = esf->a2;
7270
arch_blk.r.a3 = esf->a3;
7371
arch_blk.r.a4 = esf->a4;
7472
arch_blk.r.a5 = esf->a5;
73+
#if !defined(CONFIG_RISCV_ISA_RV32E)
74+
arch_blk.r.t3 = esf->t3;
75+
arch_blk.r.t4 = esf->t4;
76+
arch_blk.r.t5 = esf->t5;
77+
arch_blk.r.t6 = esf->t6;
7578
arch_blk.r.a6 = esf->a6;
7679
arch_blk.r.a7 = esf->a7;
80+
#endif /* !CONFIG_RISCV_ISA_RV32E */
7781
arch_blk.r.pc = esf->mepc;
7882

7983
/* Send for output */

‎arch/riscv/core/fatal.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,11 +35,17 @@ FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
3535
LOG_ERR(" a0: " PR_REG " t0: " PR_REG, esf->a0, esf->t0);
3636
LOG_ERR(" a1: " PR_REG " t1: " PR_REG, esf->a1, esf->t1);
3737
LOG_ERR(" a2: " PR_REG " t2: " PR_REG, esf->a2, esf->t2);
38+
#if defined(CONFIG_RISCV_ISA_RV32E)
39+
LOG_ERR(" a3: " PR_REG, esf->a3);
40+
LOG_ERR(" a4: " PR_REG, esf->a4);
41+
LOG_ERR(" a5: " PR_REG, esf->a5);
42+
#else
3843
LOG_ERR(" a3: " PR_REG " t3: " PR_REG, esf->a3, esf->t3);
3944
LOG_ERR(" a4: " PR_REG " t4: " PR_REG, esf->a4, esf->t4);
4045
LOG_ERR(" a5: " PR_REG " t5: " PR_REG, esf->a5, esf->t5);
4146
LOG_ERR(" a6: " PR_REG " t6: " PR_REG, esf->a6, esf->t6);
4247
LOG_ERR(" a7: " PR_REG, esf->a7);
48+
#endif /* CONFIG_RISCV_ISA_RV32E */
4349
#ifdef CONFIG_USERSPACE
4450
LOG_ERR(" sp: " PR_REG, esf->sp);
4551
#endif

‎arch/riscv/core/isr.S‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,18 @@
4545
op t0, __z_arch_esf_t_t0_OFFSET(sp) ;\
4646
op t1, __z_arch_esf_t_t1_OFFSET(sp)
4747

48+
#if defined(CONFIG_RISCV_ISA_RV32E)
49+
#define DO_CALLER_SAVED_REST(op) \
50+
op t2, __z_arch_esf_t_t2_OFFSET(sp) ;\
51+
op a0, __z_arch_esf_t_a0_OFFSET(sp) ;\
52+
op a1, __z_arch_esf_t_a1_OFFSET(sp) ;\
53+
op a2, __z_arch_esf_t_a2_OFFSET(sp) ;\
54+
op a3, __z_arch_esf_t_a3_OFFSET(sp) ;\
55+
op a4, __z_arch_esf_t_a4_OFFSET(sp) ;\
56+
op a5, __z_arch_esf_t_a5_OFFSET(sp) ;\
57+
op tp, __z_arch_esf_t_tp_OFFSET(sp) ;\
58+
op ra, __z_arch_esf_t_ra_OFFSET(sp)
59+
#else
4860
#define DO_CALLER_SAVED_REST(op) \
4961
op t2, __z_arch_esf_t_t2_OFFSET(sp) ;\
5062
op t3, __z_arch_esf_t_t3_OFFSET(sp) ;\
@@ -61,6 +73,7 @@
6173
op a7, __z_arch_esf_t_a7_OFFSET(sp) ;\
6274
op tp, __z_arch_esf_t_tp_OFFSET(sp) ;\
6375
op ra, __z_arch_esf_t_ra_OFFSET(sp)
76+
#endif /* CONFIG_RISCV_ISA_RV32E */
6477

6578
#ifdef CONFIG_SMP
6679
#define GET_CURRENT_CPU(dst, tmp) \
@@ -387,7 +400,14 @@ is_user_syscall:
387400
lr a4, __z_arch_esf_t_a4_OFFSET(sp)
388401
lr a5, __z_arch_esf_t_a5_OFFSET(sp)
389402
lr t0, __z_arch_esf_t_t0_OFFSET(sp)
403+
#if defined(CONFIG_RISCV_ISA_RV32E)
404+
/* Stack alignment for RV32E is 4 bytes */
405+
addi sp, sp, -4
406+
mv t1, sp
407+
sw t1, 0(sp)
408+
#else
390409
mv a6, sp
410+
#endif /* CONFIG_RISCV_ISA_RV32E */
391411

392412
/* validate syscall limit */
393413
li t1, K_SYSCALL_LIMIT
@@ -408,6 +428,10 @@ valid_syscall_id:
408428
/* Execute syscall function */
409429
jalr ra, t2, 0
410430

431+
#if defined(CONFIG_RISCV_ISA_RV32E)
432+
addi sp, sp, 4
433+
#endif /* CONFIG_RISCV_ISA_RV32E */
434+
411435
/* Update a0 (return value) on the stack */
412436
sr a0, __z_arch_esf_t_a0_OFFSET(sp)
413437

‎arch/riscv/core/offsets/offsets.c‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ GEN_OFFSET_SYM(_callee_saved_t, ra);
3131
GEN_OFFSET_SYM(_callee_saved_t, tp);
3232
GEN_OFFSET_SYM(_callee_saved_t, s0);
3333
GEN_OFFSET_SYM(_callee_saved_t, s1);
34+
#if !defined(CONFIG_RISCV_ISA_RV32E)
3435
GEN_OFFSET_SYM(_callee_saved_t, s2);
3536
GEN_OFFSET_SYM(_callee_saved_t, s3);
3637
GEN_OFFSET_SYM(_callee_saved_t, s4);
@@ -41,6 +42,7 @@ GEN_OFFSET_SYM(_callee_saved_t, s8);
4142
GEN_OFFSET_SYM(_callee_saved_t, s9);
4243
GEN_OFFSET_SYM(_callee_saved_t, s10);
4344
GEN_OFFSET_SYM(_callee_saved_t, s11);
45+
#endif /* !CONFIG_RISCV_ISA_RV32E */
4446

4547
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
4648
GEN_OFFSET_SYM(_callee_saved_t, fcsr);
@@ -63,18 +65,21 @@ GEN_OFFSET_SYM(z_arch_esf_t, ra);
6365
GEN_OFFSET_SYM(z_arch_esf_t, t0);
6466
GEN_OFFSET_SYM(z_arch_esf_t, t1);
6567
GEN_OFFSET_SYM(z_arch_esf_t, t2);
66-
GEN_OFFSET_SYM(z_arch_esf_t, t3);
67-
GEN_OFFSET_SYM(z_arch_esf_t, t4);
68-
GEN_OFFSET_SYM(z_arch_esf_t, t5);
69-
GEN_OFFSET_SYM(z_arch_esf_t, t6);
7068
GEN_OFFSET_SYM(z_arch_esf_t, a0);
7169
GEN_OFFSET_SYM(z_arch_esf_t, a1);
7270
GEN_OFFSET_SYM(z_arch_esf_t, a2);
7371
GEN_OFFSET_SYM(z_arch_esf_t, a3);
7472
GEN_OFFSET_SYM(z_arch_esf_t, a4);
7573
GEN_OFFSET_SYM(z_arch_esf_t, a5);
74+
75+
#if !defined(CONFIG_RISCV_ISA_RV32E)
76+
GEN_OFFSET_SYM(z_arch_esf_t, t3);
77+
GEN_OFFSET_SYM(z_arch_esf_t, t4);
78+
GEN_OFFSET_SYM(z_arch_esf_t, t5);
79+
GEN_OFFSET_SYM(z_arch_esf_t, t6);
7680
GEN_OFFSET_SYM(z_arch_esf_t, a6);
7781
GEN_OFFSET_SYM(z_arch_esf_t, a7);
82+
#endif /* !CONFIG_RISCV_ISA_RV32E */
7883

7984
GEN_OFFSET_SYM(z_arch_esf_t, mepc);
8085
GEN_OFFSET_SYM(z_arch_esf_t, mstatus);

‎arch/riscv/core/switch.S‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,13 @@
1414

1515
/* Convenience macros for loading/storing register states. */
1616

17+
#if defined(CONFIG_RISCV_ISA_RV32E)
18+
#define DO_CALLEE_SAVED(op, reg) \
19+
op ra, _thread_offset_to_ra(reg) ;\
20+
op tp, _thread_offset_to_tp(reg) ;\
21+
op s0, _thread_offset_to_s0(reg) ;\
22+
op s1, _thread_offset_to_s1(reg)
23+
#else
1724
#define DO_CALLEE_SAVED(op, reg) \
1825
op ra, _thread_offset_to_ra(reg) ;\
1926
op tp, _thread_offset_to_tp(reg) ;\
@@ -29,6 +36,7 @@
2936
op s9, _thread_offset_to_s9(reg) ;\
3037
op s10, _thread_offset_to_s10(reg) ;\
3138
op s11, _thread_offset_to_s11(reg)
39+
#endif /* CONFIG_RISCV_ISA_RV32E */
3240

3341
#define DO_FP_CALLEE_SAVED(op, reg) \
3442
op fs0, _thread_offset_to_fs0(reg) ;\

‎cmake/compiler/gcc/target_riscv.cmake‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,12 +5,19 @@ set(riscv_march "rv")
55

66
if(CONFIG_64BIT)
77
string(CONCAT riscv_mabi ${riscv_mabi} "64")
8-
string(CONCAT riscv_march ${riscv_march} "64i")
8+
string(CONCAT riscv_march ${riscv_march} "64")
99
list(APPEND TOOLCHAIN_C_FLAGS -mcmodel=medany)
1010
list(APPEND TOOLCHAIN_LD_FLAGS -mcmodel=medany)
1111
else()
1212
string(CONCAT riscv_mabi "i" ${riscv_mabi} "32")
13-
string(CONCAT riscv_march ${riscv_march} "32i")
13+
string(CONCAT riscv_march ${riscv_march} "32")
14+
endif()
15+
16+
if (CONFIG_RISCV_ISA_RV32E)
17+
string(CONCAT riscv_mabi ${riscv_mabi} "e")
18+
string(CONCAT riscv_march ${riscv_march} "e")
19+
else()
20+
string(CONCAT riscv_march ${riscv_march} "i")
1421
endif()
1522

1623
if (CONFIG_RISCV_ISA_EXT_M)

‎include/zephyr/arch/riscv/exp.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,19 +55,23 @@ struct __esf {
5555
ulong_t t0; /* Caller-saved temporary register */
5656
ulong_t t1; /* Caller-saved temporary register */
5757
ulong_t t2; /* Caller-saved temporary register */
58+
#if !defined(CONFIG_RISCV_ISA_RV32E)
5859
ulong_t t3; /* Caller-saved temporary register */
5960
ulong_t t4; /* Caller-saved temporary register */
6061
ulong_t t5; /* Caller-saved temporary register */
6162
ulong_t t6; /* Caller-saved temporary register */
63+
#endif /* !CONFIG_RISCV_ISA_RV32E */
6264

6365
ulong_t a0; /* function argument/return value */
6466
ulong_t a1; /* function argument */
6567
ulong_t a2; /* function argument */
6668
ulong_t a3; /* function argument */
6769
ulong_t a4; /* function argument */
6870
ulong_t a5; /* function argument */
71+
#if !defined(CONFIG_RISCV_ISA_RV32E)
6972
ulong_t a6; /* function argument */
7073
ulong_t a7; /* function argument */
74+
#endif /* !CONFIG_RISCV_ISA_RV32E */
7175

7276
ulong_t mepc; /* machine exception program counter */
7377
ulong_t mstatus; /* machine status register */

‎include/zephyr/sys/cbprintf_internal.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,11 @@
3030
#elif defined(__aarch64__)
3131
#define VA_STACK_MIN_ALIGN 8
3232
#elif defined(__riscv)
33+
#ifdef CONFIG_RISCV_ISA_RV32E
34+
#define VA_STACK_ALIGN(type) 4
35+
#else
3336
#define VA_STACK_MIN_ALIGN (__riscv_xlen / 8)
37+
#endif /* CONFIG_RISCV_ISA_RV32E */
3438
#endif
3539

3640
/*

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