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| 1 | +/* |
| 2 | + * Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com> |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | + #include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h> |
| 8 | + #include "apollo3_evb_connector.dtsi" |
| 9 | + |
| 10 | + &pinctrl { |
| 11 | + uart0_default: uart0_default { |
| 12 | + group1 { |
| 13 | + pinmux = <UART0TX_P22>; |
| 14 | + }; |
| 15 | + group2 { |
| 16 | + pinmux = <UART0RX_P23>; |
| 17 | + input-enable; |
| 18 | + }; |
| 19 | + }; |
| 20 | + i2c0_default: i2c0_default { |
| 21 | + group1 { |
| 22 | + pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>; |
| 23 | + drive-open-drain; |
| 24 | + drive-strength = "0.5"; |
| 25 | + bias-pull-up; |
| 26 | + }; |
| 27 | + }; |
| 28 | + i2c1_default: i2c1_default { |
| 29 | + group1 { |
| 30 | + pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>; |
| 31 | + drive-open-drain; |
| 32 | + drive-strength = "0.5"; |
| 33 | + bias-pull-up; |
| 34 | + }; |
| 35 | + }; |
| 36 | + i2c2_default: i2c2_default { |
| 37 | + group1 { |
| 38 | + pinmux = <M2SCL_P27>, <M2SDAWIR3_P25>; |
| 39 | + drive-open-drain; |
| 40 | + drive-strength = "0.5"; |
| 41 | + bias-pull-up; |
| 42 | + }; |
| 43 | + }; |
| 44 | + i2c3_default: i2c3_default { |
| 45 | + group1 { |
| 46 | + pinmux = <M3SCL_P42>, <M3SDAWIR3_P43>; |
| 47 | + drive-open-drain; |
| 48 | + drive-strength = "0.5"; |
| 49 | + bias-pull-up; |
| 50 | + }; |
| 51 | + }; |
| 52 | + i2c4_default: i2c4_default { |
| 53 | + group1 { |
| 54 | + pinmux = <M4SCL_P39>, <M4SDAWIR3_P40>; |
| 55 | + drive-open-drain; |
| 56 | + drive-strength = "0.5"; |
| 57 | + bias-pull-up; |
| 58 | + }; |
| 59 | + }; |
| 60 | + i2c5_default: i2c5_default { |
| 61 | + group1 { |
| 62 | + pinmux = <M5SCL_P48>, <M5SDAWIR3_P49>; |
| 63 | + drive-open-drain; |
| 64 | + drive-strength = "0.5"; |
| 65 | + bias-pull-up; |
| 66 | + }; |
| 67 | + }; |
| 68 | + |
| 69 | + spi0_default: spi0_default { |
| 70 | + group1 { |
| 71 | + pinmux = <M0SCK_P5>, <M0MISO_P6>, <M0MOSI_P7>; |
| 72 | + }; |
| 73 | + }; |
| 74 | + spi1_default: spi1_default { |
| 75 | + group1 { |
| 76 | + pinmux = <M1SCK_P8>, <M1MISO_P9>, <M1MOSI_P10>; |
| 77 | + }; |
| 78 | + }; |
| 79 | + spi2_default: spi2_default { |
| 80 | + group1 { |
| 81 | + pinmux = <M2SCK_P27>, <M2MISO_P25>, <M2MOSI_P28>; |
| 82 | + }; |
| 83 | + }; |
| 84 | + spi3_default: spi3_default { |
| 85 | + group1 { |
| 86 | + pinmux = <M3SCK_P42>, <M3MISO_P43>, <M3MOSI_P38>; |
| 87 | + }; |
| 88 | + }; |
| 89 | + spi4_default: spi4_default { |
| 90 | + group1 { |
| 91 | + pinmux = <M4SCK_P39>, <M4MISO_P40>, <M4MOSI_P44>; |
| 92 | + }; |
| 93 | + }; |
| 94 | + spi5_default: spi5_default { |
| 95 | + group1 { |
| 96 | + pinmux = <M5SCK_P48>, <M5MISO_P49>, <M5MOSI_P47>; |
| 97 | + }; |
| 98 | + }; |
| 99 | + |
| 100 | + adc0_default: adc0_default{ |
| 101 | + group1 { |
| 102 | + pinmux = <ADCSE4_P32>, <ADCSE7_P35>; |
| 103 | + drive-strength = "0.1"; |
| 104 | + }; |
| 105 | + }; |
| 106 | + |
| 107 | + mspi0_default: mspi0_default{ |
| 108 | + group1 { |
| 109 | + pinmux = <MSPI0_0_P22>, |
| 110 | + <MSPI0_1_P26>, |
| 111 | + <MSPI0_2_P4>, |
| 112 | + <MSPI0_3_P23>, |
| 113 | + <MSPI0_8_P24>; |
| 114 | + }; |
| 115 | + group2 { |
| 116 | + pinmux = <NCE19_P19>; |
| 117 | + drive-push-pull; |
| 118 | + drive-strength = "0.5"; |
| 119 | + ambiq,iom-nce-module = <0>; |
| 120 | + ambiq,iom-num = <6>; |
| 121 | + }; |
| 122 | + }; |
| 123 | + |
| 124 | + bleif_default: bleif_default{ |
| 125 | + group1 { |
| 126 | + pinmux = <BLEIF_SCK_P30>, |
| 127 | + <BLEIF_MISO_P31>, |
| 128 | + <BLEIF_MOSI_P32>, |
| 129 | + <BLEIF_CSN_P33>, |
| 130 | + <BLEIF_STATUS_P35>, |
| 131 | + <BLEIF_IRQ_P41>; |
| 132 | + }; |
| 133 | + }; |
| 134 | + }; |
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