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drivers: gpio: Enable support for latest GINF method
Enable support for latest GINF method which requires 3 paramters for each GPIO group and enables gpio support for intel_ptl_h platform. Signed-off-by: Anisetti Avinash Krishna <[email protected]>
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-36
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15 files changed

+25416
-36
lines changed

‎_test_plan_partial.json‎

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Large diffs are not rendered by default.

‎boards/intel/ptl/Kconfig.defconfig‎

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Original file line numberDiff line numberDiff line change
@@ -54,3 +54,11 @@ config UART_NS16550_INTEL_LPSS_DMA
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5555
config HAS_COVERAGE_SUPPORT
5656
default y
57+
58+
if GPIO
59+
config GPIO_INTEL_INT_STAT_OFFSET
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default 0x30
61+
62+
config GPIO_INTEL_INT_EN_OFFSET
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default 0x10
64+
endif

‎drivers/gpio/Kconfig.intel‎

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Original file line numberDiff line numberDiff line change
@@ -21,3 +21,26 @@ config GPIO_INTEL_CHECK_PERMS
2121
the driver allows manipulating the pin.
2222

2323
Say y if unsure.
24+
25+
config GPIO_INTEL_INT_EN_OFFSET
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hex "Offset to Interrupt Enable register from Interrupt Status register"
27+
default 0x20
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depends on GPIO_INTEL && \
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$(dt_compat_any_has_prop,$(DT_COMPAT_INTEL_GPIO),acpi-hid)
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help
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This option enables to add proper offset to access
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GPIO_INT_EN register from GPIO_INT_STAT register,
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as it is observed that the offset varies from
34+
platform to platform.
35+
36+
config GPIO_INTEL_INT_STAT_OFFSET
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hex "Offset to Interrupt Status register from General Purpose Events Status"
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default 0x40
39+
depends on GPIO_INTEL && \
40+
$(dt_compat_any_has_prop,$(DT_COMPAT_INTEL_GPIO),acpi-hid)
41+
help
42+
This option enables to add proper offset to access
43+
GPIO_INT_STAT register from General Purpose Events status
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Register, as it is observed that the offset varies from
45+
Platform to platform. GP_EVENT_STAT register is fetched
46+
from ACPI GPIO table.

‎drivers/gpio/gpio_intel.c‎

Lines changed: 23 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -125,23 +125,36 @@ struct gpio_intel_data {
125125
};
126126

127127
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
128+
#define GPIO_PAD_OWNERSHIP_SHIFT (0x04) /* Shift between Ownership regs */
129+
130+
#define GPIO_PAD_PINS_PER_REG (8) /*Pins for each Register */
131+
128132
#define GPIO_REG_BASE_GET(dev) DEVICE_MMIO_NAMED_GET(dev, reg_base)
129133

130134
#define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
131135

132-
#define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
133-
134136
#define PIN_OFFSET_GET(dev) (0)
135137

136-
#define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4)
137-
138138
#define REG_PAD_HOST_SW_OWNER_GET(data) (data)->host_owner_reg
139139

140140
#define GPIO_BASE_GET(cdf) (0)
141141

142142
#define GPIO_INTERRUPT_BASE_GET(cfg) (0)
143143

144144
#define GPIO_GET_PIN_MAX(dev) ((struct gpio_intel_data *)(dev)->data)->num_pins
145+
146+
#define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + CONFIG_GPIO_INTEL_INT_EN_OFFSET
147+
148+
#if DT_ANY_INST_HAS_BOOL_STATUS_OKAY(acpi_ginf)
149+
#define GPIO_PAD_OWNERSHIP_GET(data, pin, offset)\
150+
(data)->pad_owner_reg + (pin * GPIO_PAD_OWNERSHIP_SHIFT)
151+
152+
#else
153+
#define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg +\
154+
(((pin) / GPIO_PAD_PINS_PER_REG) * GPIO_PAD_OWNERSHIP_SHIFT)
155+
156+
#endif
157+
145158
#else /* Non-ACPI */
146159
#define GPIO_REG_BASE_GET(dev) GPIO_REG_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base))
147160

@@ -564,13 +577,14 @@ static DEVICE_API(gpio, gpio_intel_api) = {
564577
/* We need support either DTS or ACPI base resource enumeration at time.*/
565578
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid)
566579

567-
static int gpio_intel_acpi_enum(const struct device *dev, int bank_idx, char *hid, char *uid)
580+
static int gpio_intel_acpi_enum(const struct device *dev, int bank_idx, char *hid, char *uid,
581+
bool ginf)
568582
{
569583
int ret;
570584
struct gpio_acpi_res res;
571585
struct gpio_intel_data *data = dev->data;
572586

573-
ret = soc_acpi_gpio_resource_get(bank_idx, hid, uid, &res);
587+
ret = soc_acpi_gpio_resource_get(bank_idx, hid, uid, &res, ginf);
574588
if (ret) {
575589
return ret;
576590
}
@@ -605,8 +619,9 @@ static int gpio_intel_acpi_enum(const struct device *dev, int bank_idx, char *hi
605619
#define GPIO_INIT_FN_DEFINE(n) \
606620
static int gpio_intel_init##n(const struct device *dev) \
607621
{ \
608-
return gpio_intel_acpi_enum(dev, DT_INST_PROP(n, group_index), \
609-
ACPI_DT_HID(DT_DRV_INST(n)), ACPI_DT_UID(DT_DRV_INST(n))); \
622+
return gpio_intel_acpi_enum(dev, DT_INST_PROP(n, group_index), \
623+
ACPI_DT_HID(DT_DRV_INST(n)), ACPI_DT_UID(DT_DRV_INST(n)), \
624+
DT_INST_PROP(n, acpi_ginf)); \
610625
}
611626

612627
#define GPIO_MMIO_ROM_INIT(n)

‎dts/bindings/gpio/intel,gpio.yaml‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,15 @@ properties:
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type: int
2626
description: Pin offset of this GPIO entry
2727

28+
acpi-ginf:
29+
type: boolean
30+
description: |
31+
This boolean will indicate the version of GINF method ACPI
32+
enabled for a given platform. If the value is true, GINF
33+
method which takes 3 parameters (u-id,banki-id and field-id)
34+
will be used else GINF method with 2 parameters (field-id
35+
and bank-id) will be used.
36+
2837
"#gpio-cells":
2938
const: 2
3039

‎dts/x86/intel/gpio_common.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -145,6 +145,15 @@
145145
status = "disabled";
146146
};
147147

148+
gpio_v: gpio_v {
149+
compatible = "intel,gpio";
150+
interrupt-parent = <&intc>;
151+
interrupts = <ACPI_IRQ_DETECT ACPI_IRQ_FLAG_DETECT 3>;
152+
gpio-controller;
153+
#gpio-cells = <2>;
154+
status = "disabled";
155+
};
156+
148157
vgpio: vgpio {
149158
compatible = "intel,gpio";
150159
interrupt-parent = <&intc>;

‎dts/x86/intel/panther_lake_h.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -7,6 +7,8 @@
77
#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
88
#include <zephyr/dt-bindings/i2c/i2c.h>
99
#include <zephyr/dt-bindings/pcie/pcie.h>
10+
#include <zephyr/dt-bindings/gpio/gpio.h>
11+
#include "gpio_common.dtsi"
1012

1113
/ {
1214
cpus {
@@ -50,6 +52,80 @@
5052
#address-cells = <1>;
5153
};
5254

55+
acpi {
56+
gpio_a: gpio_a {
57+
acpi-hid = "INTC10BC";
58+
acpi-uid = "3";
59+
group-index = <0x02>;
60+
acpi-ginf;
61+
status = "disabled";
62+
};
63+
64+
gpio_b: gpio_b {
65+
acpi-hid = "INTC10BC";
66+
acpi-uid = "5";
67+
group-index = <0x00>;
68+
acpi-ginf;
69+
status = "disabled";
70+
};
71+
72+
gpio_c: gpio_c {
73+
acpi-hid = "INTC10BC";
74+
acpi-uid = "0";
75+
group-index = <0x01>;
76+
acpi-ginf;
77+
status = "disabled";
78+
};
79+
80+
gpio_d: gpio_d {
81+
acpi-hid = "INTC10BC";
82+
acpi-uid = "5";
83+
group-index = <0x01>;
84+
acpi-ginf;
85+
status = "disabled";
86+
};
87+
88+
gpio_e: gpio_e {
89+
acpi-hid = "INTC10BC";
90+
acpi-uid = "1";
91+
group-index = <0x01>;
92+
acpi-ginf;
93+
status = "disabled";
94+
};
95+
96+
gpio_f: gpio_f {
97+
acpi-hid = "INTC10BC";
98+
acpi-uid = "1";
99+
group-index = <0x00>;
100+
acpi-ginf;
101+
status = "disabled";
102+
};
103+
104+
gpio_h: gpio_h {
105+
acpi-hid = "INTC10BC";
106+
acpi-uid = "3";
107+
group-index = <0x01>;
108+
acpi-ginf;
109+
status = "disabled";
110+
};
111+
112+
gpio_s: gpio_s {
113+
acpi-hid = "INTC10BC";
114+
acpi-uid = "4";
115+
group-index = <0x00>;
116+
acpi-ginf;
117+
status = "disabled";
118+
};
119+
120+
gpio_v: gpio_v {
121+
acpi-hid = "INTC10BC";
122+
acpi-uid = "0";
123+
group-index = <0x00>;
124+
acpi-ginf;
125+
status = "disabled";
126+
};
127+
};
128+
53129
pcie0: pcie0 {
54130
#address-cells = <1>;
55131
#size-cells = <1>;
@@ -179,6 +255,7 @@
179255
pw,cs-mode = <0>;
180256
pw,cs-output = <0>;
181257
pw,fifo-depth = <64>;
258+
cs-gpios = <&gpio_e 17 GPIO_ACTIVE_LOW>;
182259
clock-frequency = <100000000>;
183260
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
184261
interrupt-parent = <&intc>;
@@ -194,6 +271,7 @@
194271
pw,cs-mode = <0>;
195272
pw,cs-output = <0>;
196273
pw,fifo-depth = <64>;
274+
cs-gpios = <&gpio_f 17 GPIO_ACTIVE_LOW>;
197275
clock-frequency = <100000000>;
198276
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
199277
interrupt-parent = <&intc>;
@@ -209,6 +287,7 @@
209287
pw,cs-mode = <0>;
210288
pw,cs-output = <0>;
211289
pw,fifo-depth = <64>;
290+
cs-gpios = <&gpio_f 18 GPIO_ACTIVE_LOW>;
212291
clock-frequency = <100000000>;
213292
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
214293
interrupt-parent = <&intc>;

‎soc/intel/alder_lake/CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -8,6 +8,6 @@ zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
88
zephyr_cc_option(-march=goldmont)
99

1010
zephyr_library_sources(cpu.c)
11-
zephyr_library_sources(../common/soc_gpio.c)
11+
zephyr_library_sources_ifdef(CONFIG_GPIO ../common/soc_gpio.c)
1212

1313
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

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