dts: arm: nxp: lpc: Add dts nodes for IOCON

Add binding and dts nodes for the IOCON and IOCON ports on the LPC
family of SoCs.

Signed-off-by: Kumar Gala <[email protected]>

Author: galak

dts/arm/nxp/nxp_lpc54xxx.dtsi

@@ -79,6 +79,22 @@
 			};
 		};
 
+		iocon: iocon@40001000 {
+			compatible = "nxp,lpc-iocon";
+			reg = <0x40001000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x40001000 0x100>;
+			pio0: pio0@0 {
+				compatible = "nxp,lpc-iocon-pio";
+				reg = <0x0 0x80>;
+			};
+			pio1: pio0@80 {
+				compatible = "nxp,lpc-iocon-pio";
+				reg = <0x80 0x80>;
+			};
+		};
+
 		gpio0: gpio@0 {
 			compatible = "nxp,lpc-gpio";
 			reg = <0x4008c000 0x2488>;

dts/arm/nxp/nxp_lpc55S1x_common.dtsi

@@ -99,6 +99,22 @@
 		};
 	};
 
+	iocon: iocon@1000 {
+		compatible = "nxp,lpc-iocon";
+		reg = <0x1000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x1000 0x100>;
+		pio0: pio0@0 {
+			compatible = "nxp,lpc-iocon-pio";
+			reg = <0x0 0x80>;
+		};
+		pio1: pio0@80 {
+			compatible = "nxp,lpc-iocon-pio";
+			reg = <0x80 0x80>;
+		};
+	};
+
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;

dts/arm/nxp/nxp_lpc55S2x_common.dtsi

@@ -100,6 +100,22 @@
 		};
 	};
 
+	iocon: iocon@1000 {
+		compatible = "nxp,lpc-iocon";
+		reg = <0x1000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x1000 0x100>;
+		pio0: pio0@0 {
+			compatible = "nxp,lpc-iocon-pio";
+			reg = <0x0 0x80>;
+		};
+		pio1: pio0@80 {
+			compatible = "nxp,lpc-iocon-pio";
+			reg = <0x80 0x80>;
+		};
+	};
+
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;

dts/arm/nxp/nxp_lpc55S6x_common.dtsi

@@ -114,6 +114,22 @@
 		};
 	};
 
+	iocon: iocon@1000 {
+		compatible = "nxp,lpc-iocon";
+		reg = <0x1000 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x1000 0x100>;
+		pio0: pio0@0 {
+			compatible = "nxp,lpc-iocon-pio";
+			reg = <0x0 0x80>;
+		};
+		pio1: pio0@80 {
+			compatible = "nxp,lpc-iocon-pio";
+			reg = <0x80 0x80>;
+		};
+	};
+
 	gpio0: gpio@0 {
 		compatible = "nxp,lpc-gpio";
 		reg = <0x8c000 0x2488>;

dts/bindings/pinctrl/nxp,lpc-iocon-pio.yaml

@@ -0,0 +1,12 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC I/O Pin Configuration (IOCON) Port I/O (PIO)
+
+compatible: "nxp,lpc-iocon-pio"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true

dts/bindings/pinctrl/nxp,lpc-iocon.yaml

@@ -0,0 +1,12 @@
+# Copyright (c) 2021, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC I/O Pin Configuration (IOCON)
+
+compatible: "nxp,lpc-iocon"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true