soc: riscv: riscv-privileged: drop soc_common.h

gmarull · carlescufi · commit 6876f9eea1ac · 2024-01-15T09:58:03.000+01:00
The header file is no longer needed.

Signed-off-by: Gerard Marull-Paretas &lt;gerard@teslabs.com&gt;
diff --git a/soc/riscv/andes_v5/ae350/soc.h b/soc/riscv/andes_v5/ae350/soc.h
@@ -11,8 +11,6 @@
 #ifndef __RISCV_ANDES_AE350_SOC_H_
 #define __RISCV_ANDES_AE350_SOC_H_
 
-#include <soc_common.h>
-
 /* Include CSRs available for Andes V5 SoCs */
 #include "soc_v5.h"
 
diff --git a/soc/riscv/common/riscv-privileged/soc_common.h b/soc/riscv/common/riscv-privileged/soc_common.h
diff --git a/soc/riscv/efinix_sapphire/soc.h b/soc/riscv/efinix_sapphire/soc.h
@@ -7,7 +7,6 @@
 #ifndef __RISCV32_EFINIX_SAPPHIRE_SOC_H_
 #define __RISCV32_EFINIX_SAPPHIRE_SOC_H_
 
-#include "soc_common.h"
 #include <zephyr/arch/riscv/sys_io.h>
 #include <zephyr/devicetree.h>
 
diff --git a/soc/riscv/gd_gd32/gd32vf103/soc.h b/soc/riscv/gd_gd32/gd32vf103/soc.h
@@ -11,6 +11,4 @@
 #ifndef RISCV_GD32VF103_SOC_H_
 #define RISCV_GD32VF103_SOC_H_
 
-#include <soc_common.h>
-
 #endif  /* RISCV_GD32VF103_SOC_H */
diff --git a/soc/riscv/intel_niosv/niosv/soc.h b/soc/riscv/intel_niosv/niosv/soc.h
@@ -7,7 +7,6 @@
 #ifndef RISCV_INTEL_FPGA_NIOSV_H
 #define RISCV_INTEL_FPGA_NIOSV_H
 
-#include <soc_common.h>
 #include <zephyr/devicetree.h>
 
 #endif /* RISCV_INTEL_FPGA_NIOSV_H */
diff --git a/soc/riscv/litex_vexriscv/soc.h b/soc/riscv/litex_vexriscv/soc.h
@@ -7,7 +7,6 @@
 #ifndef __RISCV32_LITEX_VEXRISCV_SOC_H_
 #define __RISCV32_LITEX_VEXRISCV_SOC_H_
 
-#include "../common/riscv-privileged/soc_common.h"
 #include <zephyr/devicetree.h>
 #include <zephyr/arch/riscv/sys_io.h>
 
diff --git a/soc/riscv/microchip_miv/miv/soc.h b/soc/riscv/microchip_miv/miv/soc.h
@@ -4,8 +4,6 @@
 #ifndef __RISCV32_MIV_SOC_H_
 #define __RISCV32_MIV_SOC_H_
 
-#include <soc_common.h>
-
 /* UART Configuration */
 #define MIV_UART_0_LINECFG           0x1
 
diff --git a/soc/riscv/microchip_miv/polarfire/soc.h b/soc/riscv/microchip_miv/polarfire/soc.h
@@ -6,7 +6,6 @@
 #ifndef __RISCV64_MPFS_SOC_H_
 #define __RISCV64_MPFS_SOC_H_
 
-#include <soc_common.h>
 #include <zephyr/devicetree.h>
 
 
diff --git a/soc/riscv/neorv32/soc.h b/soc/riscv/neorv32/soc.h
@@ -7,8 +7,6 @@
 #ifndef RISCV_NEORV32_SOC_H
 #define RISCV_NEORV32_SOC_H
 
-#include <soc_common.h>
-
 /* System information (SYSINFO) register offsets */
 #define NEORV32_SYSINFO_CLK         0x00U
 #define NEORV32_SYSINFO_CPU         0x04U
diff --git a/soc/riscv/opentitan/soc.h b/soc/riscv/opentitan/soc.h
@@ -7,7 +7,6 @@
 #ifndef __RISCV_OPENTITAN_SOC_H_
 #define __RISCV_OPENTITAN_SOC_H_
 
-#include <soc_common.h>
 #include <zephyr/devicetree.h>
 
 /* OpenTitan power management regs. */
diff --git a/soc/riscv/renode_virt/soc.h b/soc/riscv/renode_virt/soc.h
@@ -7,6 +7,4 @@
 #ifndef __RISCV32_RENODE_SOC_H_
 #define __RISCV32_RENODE_SOC_H_
 
-#include <soc_common.h>
-
 #endif /* __RISCV32_RENODE_SOC_H_ */
diff --git a/soc/riscv/sifive_freedom/e300/soc.h b/soc/riscv/sifive_freedom/e300/soc.h
@@ -11,8 +11,6 @@
 #ifndef __RISCV_SIFIVE_FREEDOM_FE300_SOC_H_
 #define __RISCV_SIFIVE_FREEDOM_FE300_SOC_H_
 
-#include <soc_common.h>
-
 /* PINMUX MAX PINS */
 #define SIFIVE_PINMUX_PINS            32
 
diff --git a/soc/riscv/sifive_freedom/u500/soc.h b/soc/riscv/sifive_freedom/u500/soc.h
@@ -11,8 +11,6 @@
 #ifndef __RISCV_SIFIVE_FREEDOM_U500_SOC_H_
 #define __RISCV_SIFIVE_FREEDOM_U500_SOC_H_
 
-#include <soc_common.h>
-
 /* Clock controller. */
 #define PRCI_BASE_ADDR               0x10000000
 
diff --git a/soc/riscv/sifive_freedom/u700/soc.h b/soc/riscv/sifive_freedom/u700/soc.h
@@ -11,8 +11,6 @@
 #ifndef __RISCV_SIFIVE_FREEDOM_U700_SOC_H_
 #define __RISCV_SIFIVE_FREEDOM_U700_SOC_H_
 
-#include <soc_common.h>
-
 /* Clock controller. */
 #define PRCI_BASE_ADDR               0x10000000
 
diff --git a/soc/riscv/starfive_jh71xx/jh71xx/soc.h b/soc/riscv/starfive_jh71xx/jh71xx/soc.h
@@ -7,6 +7,4 @@
 #ifndef __RISCV_VIRT_SOC_H_
 #define __RISCV_VIRT_SOC_H_
 
-#include <soc_common.h>
-
 #endif
diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc.h b/soc/riscv/telink_tlsr/tlsr951x/soc.h
@@ -7,6 +7,4 @@
 #ifndef RISCV_TELINK_B91_SOC_H
 #define RISCV_TELINK_B91_SOC_H
 
-#include <soc_common.h>
-
 #endif /* RISCV_TELINK_B91_SOC_H */
diff --git a/soc/riscv/virt/soc.h b/soc/riscv/virt/soc.h
@@ -7,8 +7,6 @@
 #ifndef __RISCV_VIRT_SOC_H_
 #define __RISCV_VIRT_SOC_H_
 
-#include <soc_common.h>
-
 #define SIFIVE_SYSCON_TEST           0x00100000
 #define RISCV_MSIP_BASE              0x02000000
 
