@@ -137,18 +137,13 @@ static inline int qspi_prepare_quad_read(const struct device *dev,
137137{
138138 struct flash_stm32_qspi_data * dev_data = dev -> data ;
139139
140- switch (dev_data -> mode ) {
141- case JESD216_MODE_114 :
142- cmd -> AddressMode = QSPI_ADDRESS_1_LINE ;
143- break ;
144- case JESD216_MODE_144 :
145- cmd -> AddressMode = QSPI_ADDRESS_4_LINES ;
146- break ;
147- default :
148- return - ENOTSUP ;
149- }
140+ __ASSERT_NO_MSG (dev_data -> mode == JESD216_MODE_114 ||
141+ dev_data -> mode == JESD216_MODE_144 );
150142
151143 cmd -> Instruction = dev_data -> qspi_read_cmd ;
144+ cmd -> AddressMode = ((dev_data -> mode == JESD216_MODE_114 )
145+ ? QSPI_ADDRESS_1_LINE
146+ : QSPI_ADDRESS_4_LINES );
152147 cmd -> DataMode = QSPI_DATA_4_LINES ;
153148 cmd -> DummyCycles = dev_data -> qspi_read_cmd_latency ;
154149
@@ -160,19 +155,13 @@ static inline int qspi_prepare_quad_program(const struct device *dev,
160155{
161156 struct flash_stm32_qspi_data * dev_data = dev -> data ;
162157
163- cmd -> Instruction = dev_data -> qspi_write_cmd ;
164-
165- switch (cmd -> Instruction ) {
166- case SPI_NOR_CMD_PP_1_1_4 :
167- cmd -> AddressMode = QSPI_ADDRESS_1_LINE ;
168- break ;
169- case SPI_NOR_CMD_PP_1_4_4 :
170- cmd -> AddressMode = QSPI_ADDRESS_4_LINES ;
171- break ;
172- default :
173- return - ENOTSUP ;
174- }
158+ __ASSERT_NO_MSG (dev_data -> qspi_write_cmd == SPI_NOR_CMD_PP_1_1_4 ||
159+ dev_data -> qspi_write_cmd == SPI_NOR_CMD_PP_1_4_4 );
175160
161+ cmd -> Instruction = dev_data -> qspi_write_cmd ;
162+ cmd -> AddressMode = ((cmd -> Instruction == SPI_NOR_CMD_PP_1_1_4 )
163+ ? QSPI_ADDRESS_1_LINE
164+ : QSPI_ADDRESS_4_LINES );
176165 cmd -> DataMode = QSPI_DATA_4_LINES ;
177166 cmd -> DummyCycles = 0 ;
178167
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