tests: drivers: add fracn test for stm32h7 clock configuration tests

add overlay to use fracn with HSI in clock configuration tests for
stm32h7

Signed-off-by: Nathan Olff <[email protected]>

Author: nono313

tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 Kickmaker
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	hsi-div = <1>;		/* HSI RC: 64MHz, hsi_clk = 64MHz */
+	status = "okay";
+};
+
+&pll {
+	div-m = <4>;
+	mul-n = <34>;
+	div-p = <1>;
+	div-q = <4>;
+	div-r = <2>;
+	clocks = <&clk_hsi>;
+	fracn = <3072>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(550)>;
+	d1cpre = <1>;
+	hpre = <2>;
+	d1ppre = <2>;
+	d2ppre1 = <2>;
+	d2ppre2 = <2>;
+	d3ppre = <2>;
+};

tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml

@@ -46,3 +46,10 @@ tests:
       - stm32h735g_disco
     integration_platforms:
       - nucleo_h723zg
+  drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_pll_hsi_fracn_550:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_fracn_550.overlay"
+    platform_allow:
+      - nucleo_h723zg
+      - stm32h735g_disco
+    integration_platforms:
+      - nucleo_h723zg